Patents Assigned to TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.
  • Publication number: 20230242115
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor For Manufactuing Co., Ltd.
    Inventors: Ting-Ting CHEN, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
  • Patent number: 10651079
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia