Patents Assigned to Taiwan Semiconductor Manufactuing Company, Ltd.
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Patent number: 10163476Abstract: A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.Type: GrantFiled: March 16, 2018Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang
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Patent number: 10156783Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.Type: GrantFiled: February 27, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
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Patent number: 9666520Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: GrantFiled: August 19, 2014Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Patent number: 9660033Abstract: A method of semiconductor device fabrication includes providing a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first layer, a second layer over the first layer, and a third layer over the second layer. A gap is formed by removing at least a portion of the second layer from the channel region. A first material is formed in the channel region to form first and second interfacial layer portions, each at least partially wrapping around the first and third layers respectively. A second material is deposited in the channel region to form first and second high-k dielectric layer portions, each at least partially wrapping around the first and second interfacial layer portions. A metal layer including a scavenging material is formed along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region.Type: GrantFiled: January 13, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: I-Sheng Chen, Chih Chieh Yeh, Cheng-Hsien Wu, Yee-Chia Yeo
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Patent number: 9236856Abstract: An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits.Type: GrantFiled: December 9, 2010Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Justin Shi, Alan Roth, Ying-Chih Hsu, Justin Gaither, Eric Soenen
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Publication number: 20150145579Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.Inventors: Chih-Chang LIN, Chan-Hong CHERN, Tsung-Ching HUANG, Ming-Chieh HUANG
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Publication number: 20140151698Abstract: An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen
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Patent number: 8580117Abstract: System and method for replacing a resist filter in such a manner as to reduce filter-induced wafer defects are described. In one embodiment, the system comprises a filtration system connected to a dispenser, the filtration system comprising a filter; and a switch connected to the filter for selectively connecting the filtration system to throughput one of a first chemical solution and a second chemical solution.Type: GrantFiled: March 20, 2007Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Yao-Hwan Kao, Po-Chang Huang
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Patent number: 8219951Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.Type: GrantFiled: February 26, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Chih-Wei Hsu, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang, Boren Luo
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Publication number: 20120125747Abstract: The present disclosure provides in one embodiment, a semiconductor device that includes a MEMS switch having a substrate, a first dielectric layer disposed above the substrate, and a bottom signal electrode, a bump, and a bottom actuation electrode disposed above the first dielectric layer. The MEMS switch further includes a second dielectric layer enclosing the bottom signal electrode, and a movable member including a top signal electrode disposed above the bottom signal electrode and a top actuation electrode disposed above the bottom actuation electrode and the bump, wherein the top actuation electrode is electrically coupled to the bump. A method of fabricating a MEMS switch is also disclosed.Type: ApplicationFiled: November 22, 2010Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.Inventors: Chia-Hua Chu, Chung-Hsien Lin, Chun-Wen Cheng