Abstract: A cup wash disk for cleaning a photoresist process tool is provided. An upper plate is arranged over a lower plate to define a cavity between the upper and lower plates. The lower plate comprises peripheral openings in fluid communication with the cavity and arranged along a periphery of the lower plate. A plurality of shims is arranged between the upper and lower plates to space the upper and lower plates and to define slits between the upper and lower plates. The slits are in fluid communication with the cavity. A method for cleaning the photoresist process tool using the cup wash disk is also provided.

Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; providing a mixture of phosphoric acid and a silicon-containing material; and delivering the mixture to the surface of the wafer to remove the silicon nitride. Single wafer etching apparatuses of selectively removing silicon nitride are also provided.

Abstract: An apparatus includes an ionization chamber and an electron source device at least partially disposed inside the ionization chamber. The ionization chamber is configured to receive at least one chemical and provide plasma having ionized chemicals. The electron source device includes at least one filament configured to generate electrons, and a cathode configured to emit secondary electrons from the front surface when the electrons from the at least one filament hit the back surface of the cathode. The front surface of the cathode is shaped convex facing inside the ionization chamber.

Abstract: Structures and formation methods of a light sensing device are provided. The light sensing device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The light sensing device also includes a filter element over the semiconductor substrate and aligned with the light sensing region. The filter element has a first portion and a second portion, and the first portion is between the second portion and the light sensing region. The light sensing device further includes a light shielding element over the semiconductor substrate and beside the first portion of the filter element. In addition, the light sensing device includes a dielectric element over the light shielding element and beside the second portion of the filter element. A top width of the light shielding element is greater than a bottom width of the dielectric element.

Abstract: A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.

Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a first top plane and the source/drain structure has a second top plane. The first top plane of the cap element is wider than the second top plane of the source/drain structure. A surface orientation of the first top plane of the cap element and a surface orientation of a side surface of the cap element are different from each other.

Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: A device includes memory cells, a first reference switch, a second reference switch, a first reference storage unit, a second reference storage unit, and an average current circuit. The memory cells are each configured to store corresponding bit data. The first reference switch and the second reference switch are turned on when a word line is activated. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The average current circuit averages the first signal and the second signal to generate a reference signal to be compared with a current indicating the bit data of one memory cell, in order to determine a logic state of the bit data of the memory cell.

Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.