Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
  • Patent number: 10410715
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 10386879
    Abstract: A bandgap reference voltage circuit includes a bandgap reference voltage generator and a startup current generator. The bandgap reference voltage generator is configured to generate a first voltage and a second voltage. The startup current generator includes a voltage comparator and a switch. The voltage comparator is connected to the bandgap reference voltage generator and is configured to compare the first voltage with the sum of the second voltage and an offset voltage and to generate a comparison result. The switch is connected between the voltage comparator and the bandgap reference voltage generator and is configured to selectively connect a supply voltage to the bandgap reference voltage generator based on the comparison result. A device that includes the circuit is also disclosed. A method of operating the circuit is also disclosed.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Lun Yen, Cheng-Hsiung Kuo
  • Patent number: 10373865
    Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Chen-Yuan Chen, Ho-Chun Liou, Yi-Te Chen
  • Patent number: 10367063
    Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hao-Ling Tang, Jon-Hsu Ho, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai
  • Patent number: 10354998
    Abstract: Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Yung-Ta Li, Chun-Hsiang Fan, Tung-Ying Lee, Clement Hsing-Jen Wann
  • Patent number: 10354719
    Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
  • Patent number: 10354741
    Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mei-Chen Chuang, Alan Roth
  • Patent number: 10355527
    Abstract: At least one of a system or a method for wirelessly charging a device is provided. A wireless receiver is configured to communicate with a device to be charged to determine a desired charge scenario indicative of power to be supplied to the device. Based upon the desired charge scenario, a resonant frequency of the wireless receiver is set. The resonant frequency, in combination with energy transferred from a wireless transmitter, is configured to induce a current in the wireless receiver. Power is supplied to the device based upon the current induced in the wireless receiver.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chung Tseng, Alan Roth, Eric Soenen
  • Patent number: 10347746
    Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tetsu Ohtou, Jiun-Peng Wu, Ching-Wei Tsai
  • Patent number: 10340300
    Abstract: Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. A filler grid is formed over the photodiode array, such as over a dielectric grid. The filler grid comprises one or more filler structures, such as a first filler structure that provides a light propagation path to a first photodiode that is primarily through the first filler structure. In this way, signal strength decay of light along the light propagation path before detection by the first photodiode is mitigated. The image sensor comprises a reflective layer that channels light towards corresponding photodiodes. For example, a first reflective layer portion guides light towards the first photodiode and away from a second photodiode. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Chi-Cherng Jeng, Chen Hsin-Chi, Shih-Ciang Huang, Wang Chun-Ying, Volume Chien, Zhe-Ju Liu
  • Patent number: 10340004
    Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Cheng Chou
  • Patent number: 10340301
    Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Volume Chien, Yun-Wei Cheng, I-I Cheng, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 10340919
    Abstract: Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shao-Yu Li, Shao-Te Wu
  • Patent number: 10340218
    Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Patent number: 10340192
    Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shiu-Ko Jangjian, Ren-Hau Yu, Chi-Cherng Jeng
  • Patent number: 10325989
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10322930
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10319435
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10319423
    Abstract: A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
  • Patent number: 10312338
    Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh