Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
  • Patent number: 12224268
    Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 12224352
    Abstract: A thin film transistor includes a stack of an active layer, a gate dielectric, and a gate electrode in a forward or in a reverse order. The active layer includes a compound semiconductor material containing oxygen, at least one acceptor-type element selected from Ga and W, and at least one heavy post-transition metal element selected from In and Sn. An atomic percentage of the at least one heavy post-transition metal element at a first surface portion of the active layer that contacts the gate dielectric is higher than an atomic percentage of the at least one heavy post-transition metal element at a second surface portion of the active layer located on an opposite side of the gate dielectric. The front channel current may be increased, and the back channel leakage current may be decreased.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Hai-Ching Chen, Po-Ting Lin
  • Patent number: 12219748
    Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kam-Tou Sio, Yi-Hsun Chiu
  • Patent number: 12218253
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: April 15, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Yi-Ling Liu, Huai-Jen Tung, Keng-Ying Liao
  • Patent number: 12219778
    Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Patent number: 12217992
    Abstract: Methods and systems for improving the efficiency of an automated material handling system (AMHS) include providing an apparatus operatively coupled to a load port of a processing apparatus, where the apparatus is configured to remove a first work-in-process from the load port and to move the first work-in-process along a first direction to displace the first work-in-progress from the load port while a second work-in-progress is transferred to the load port from an AMHS vehicle along a second direction that is perpendicular to the first direction, and transferring the first work-in-progress to an AMHS vehicle along the second direction. The methods and systems may be used for loading and unloading wafer storage containers, such as front opening unified pods (FOUPs), in a semiconductor fabrication facility.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Yen-Fu Shen
  • Patent number: 12219780
    Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Chung Ho, Hui-Hsien Wei, Mauricio Manfrini, Chia-Jung Yu, Yong-Jie Wu, Ken-Ichi Goto, Pin-Cheng Hsu
  • Patent number: 12218250
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 12218141
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 12219882
    Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsing-Hsiang Wang, Yu-Feng Yin, Jiann-Horng Lin, Huan-Just Lin
  • Patent number: 12211568
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 12211869
    Abstract: An image sensor includes an array of image pixels and black level correction (BLC) pixels. Each BLC pixel includes a BLC pixel photodetector, a BLC pixel sensing circuit, and a BLC pixel optics assembly configured to block light that impinges onto the BLC pixel photodetector. Each BLC pixel optics assembly may include a first portion of a layer stack including a vertically alternating sequence of first material layers having a first refractive index and second material layers having a second refractive index. Additionally or alternatively, each BLC pixel optics assembly may include a first portion of a layer stack including at least two metal layers, each having a respective wavelength sub-range having a greater reflectivity than another metal layer. Alternatively or additionally, each BLC pixel optics assembly may include an infrared blocking material layer that provides a higher absorption coefficient than color filter materials within image pixel optics assemblies.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 12211574
    Abstract: Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Katherine H. Chiang
  • Patent number: 12204364
    Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Wei Chih Chen
  • Patent number: 12206024
    Abstract: A transistor includes a vertical stack containing, in order from bottom to top or from top to bottom, a gate electrode, a gate dielectric, and an active layer and located over a substrate. The active layer includes an amorphous semiconductor material. A crystalline source region including a first portion of a crystalline semiconductor material overlies, and is electrically connected to, a first end portion of the active layer. A crystalline drain region including a second portion of the crystalline semiconductor material overlies, and is electrically connected to, a second end portion of the active layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Georgios Vellianitis, Marcus Johannes Henricus Van Dal, Gerben Doornbos, Mauricio Manfrini
  • Patent number: 12205901
    Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jheng-Hong Jiang, Chia-Wei Liu, Shing-Huang Wu
  • Patent number: 12198956
    Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tsung-Sheng Kuo, Chih-Chun Chiu, Chih-Chieh Fu, Chueng-Jen Wang, Hsuan Lee, Jiun-Rong Pai
  • Patent number: 12199159
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Grant
    Filed: June 19, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Huai-Jen Tung, Keng-Ying Liao
  • Patent number: 12199188
    Abstract: A stack including an active layer, a gate dielectric, and a gate electrode is formed in a forward or in a reverse order, over a substrate. The active layer includes a front channel layer, a bulk semiconductor layer, and a back channel layer. The front channel layer is formed by depositing a layer stack that include at least one post-transition metal oxide layer, a zinc oxide layer, and at least one acceptor-type oxide layer. The zinc oxide layer or at least one post transition metal oxide layer contacts the gate dielectric, and the at least one acceptor-type oxide layer is most distal from the gate dielectric. The front channel layer provides enhanced channel conductivity, while the back channel layer provides suppressed channel conductivity.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 12196780
    Abstract: A probe assembly includes a multilayer structure including probe contact pads, an upper guide plate including an array of upper holes therethrough, a lower guide plate including an array of lower holes therethrough, a vertical stack of a plurality of dielectric spacer plates located between the upper guide plate and the lower guide plate and including a respective opening therethrough, and an array of probes attached to the probe contact pads, vertically extending through the array of upper holes and the array of lower holes, and vertically extending through the openings through the vertical stack of the plurality of dielectric spacer plates.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Cheng Hsu, Wen-Chun Tu