Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
  • Patent number: 11514982
    Abstract: A ferroelectric computation unit includes a first ferroelectric switching device that includes a first ferroelectric material portion and generates a digital output signal, and a second ferroelectric switching device that includes a second ferroelectric material portion and generates an analog output signal. An output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to a gate electrode of another of the first ferroelectric switching device and the second ferroelectric switching device to provide hybrid response characteristics of stochastic digital switching and analog switching.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11515355
    Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LIMITED
    Inventors: Yeh-Hsun Fang, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11515313
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 11509346
    Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho, William Wu Shen
  • Publication number: 20220366972
    Abstract: Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
  • Patent number: 11500151
    Abstract: A semiconductor arrangement is provided and includes a first dielectric layer over an optical device. A first metallization layer is over the first dielectric layer, and a first conductive line is in the first metallization layer. A first conductive via is in the first metallization layer and contacts the first conductive line. A second metallization layer is over the first metallization layer. A second conductive line is in the second metallization layer and contacts the first conductive via at a first interface. A heater is over the optical device and has a lowermost surface below the first interface and an uppermost surface above the first interface.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chan-Hong Chern
  • Publication number: 20220359288
    Abstract: A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsui-Ling Yen, Chien-Hung Chen
  • Publication number: 20220359713
    Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
  • Publication number: 20220359606
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Publication number: 20220358275
    Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Jiann-Tyng Tzeng, Lipen Yuan, Hui-Zhong Zhuang, Yu-Xuan Huang
  • Patent number: 11495497
    Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
  • Patent number: 11495314
    Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hao Huang, Cheng-Yi Wu, Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11489530
    Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20220344491
    Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao LIN, Tzu-Chung Wang, Shu-Yuan Ku
  • Patent number: 11482276
    Abstract: A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hidehiro Fujiwara, Yi-Hsun Chiu, Yih Wang
  • Patent number: 11482506
    Abstract: A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Hsin-Chi Chen, Kuo-Cheng Lee, Mu-Han Cheng, Yun-Wei Cheng
  • Publication number: 20220334842
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kai-Chi Huang, Chi-Lin Liu, Wei-Hsiang Ma, Shang-Chih Hsieh
  • Publication number: 20220335194
    Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Limited
    Inventors: Sheng-Hsiung Chen, Jerry Kao, Kuo-Nan Yang, Jack Liu
  • Publication number: 20220328646
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen