Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
  • Patent number: 11189546
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Josh Lin, Chung-Jen Huang, Yun-Chi Wu, Tsung-Yu Yang
  • Patent number: 11189560
    Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Patent number: 11189653
    Abstract: A semiconductor device includes a pixel array comprising a first pixel and a second pixel. The semiconductor device includes a metal structure overlying a portion of a substrate between the first pixel and the second pixel. The semiconductor device includes a first barrier layer adjacent a sidewall of the metal structure. The semiconductor device includes a passivation layer adjacent a sidewall of the first barrier layer. The first barrier layer is between the passivation layer and the metal structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ya Chun Teng, Yun-Wei Cheng, Chien Ming Sung
  • Patent number: 11189524
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20210367034
    Abstract: A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Publication number: 20210366909
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J.H. Wang
  • Publication number: 20210366822
    Abstract: A hybrid via interconnect structure includes a first metal filling at least partially surrounded by a first barrier metal layer, a second metal filling at least partially surrounded by a second barrier metal layer, and a hybrid via formed between the first metal filling and the second metal filling. The hybrid via provides an electrical connection between the first metal filling and the second metal filling and is formed of a different material than the first metal filling, the second metal filling, the first barrier metal layer, and the second barrier metal layer. The hybrid via interconnect structure can be formed during the back end of line (BEOL) portion of an integrated circuit (IC) fabrication process to provide reduced interconnect resistance and improved ease of fabrication.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Lung Chung, Shin-Yi Yang, Ming-Han Lee
  • Publication number: 20210366752
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a first loading tray configured to couple to a first wafer holding device holding a plurality of wafers. The first wafer holding device includes a first opening. The apparatus includes a second loading tray configured to couple to a second wafer holding device. The second wafer holding device includes a second opening. The apparatus includes a first motor coupled to the first loading tray and configured to rotate the first wafer holding device until the first opening faces the second opening to allow transfer of the plurality of wafers from the first wafer holding device to the second wafer holding device.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chung-Hsung Yang, Yung-Ho Chen
  • Patent number: 11183572
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Patent number: 11183504
    Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chenchen Jacob Wang, Yu-Ming Lin, Chi On Chui, Sai-Hooi Yeong, Bo-Feng Young
  • Patent number: 11180363
    Abstract: A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuei-Sung Chang, Tai-Bang An, Chun-wen Cheng, Hung-Hua Lin
  • Publication number: 20210358901
    Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jack Liu
  • Patent number: 11177368
    Abstract: Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Chieh Chen, Hao-Hsiung Lin, Shu-Han Chen, You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11177435
    Abstract: A via-level dielectric material layer is formed over a first dielectric material layer embedding a first conductive structure. A via cavity is formed through the via-level dielectric material layer. A least one straight sidewall vertically extends from a closed upper periphery of the via cavity at a top surface of the via-level dielectric material layer to a closed lower periphery of the via cavity that is adjoined to a top surface of the first conductive structure. A pillar stack structure is formed in the via cavity by sequentially forming a set of material portions containing a lower pillar structure and an upper pillar structure. The lower pillar structure and the upper pillar structure include a selector material pillar and a memory material pillar. A second conductive structure may be formed on a top surface of the pillar stack structure. The pillar stack structure may be used in an array configuration.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Xinyu Bao, Hon-Sum Philip Wong
  • Patent number: 11177177
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. A first layer is formed over a semiconductor layer, and a first patterned mask is formed over the first layer. A cyclic etch process is then performed to define a second patterned mask in the first layer. The cyclic etch process includes a first phase to form a polymer layer over the first patterned mask and a second phase to remove the polymer layer and to remove a portion of the first layer. A portion of the semiconductor layer is removed using the second patterned mask to define a fin from the semiconductor layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Fo-Ju Lin, Chia-Wei Chang, Chiung Wen Hsu
  • Patent number: 11177306
    Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Volume Chien, Yun-Wei Cheng, I-I Cheng, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 11172156
    Abstract: An image sensor includes a photosensitive sensor, a floating diffusion node, a reset transistor, and a source follower transistor. The reset transistor comprises a first source/drain coupled to the floating diffusion node and a second source/drain coupled to a first voltage source. The source follower transistor comprises a gate coupled to the floating diffusion node and a first source/drain coupled to the second source/drain of the reset transistor. A first elongated contact contacts the second source/drain of the reset transistor and the first source/drain of the source follower transistor. The first elongated contact has a first dimension in a horizontal cross-section and a second dimension in the horizontal cross-section. The second dimension is perpendicular to the first dimension, and the second dimension is less than the first dimension.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yun-Wei Cheng, Chia Chun-Wei, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11167982
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 11171138
    Abstract: A semiconductor arrangement includes a well region, a transistor over the well region, a conductive line in conductive contact with a first source/drain region of the transistor and having a sidewall in conductive contact with a sidewall of the well region, and a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region. A method includes forming a well region in a semiconductor layer. A first fin and a second fin are formed over the well region. A first spacer is formed on the first fin and a second spacer is formed on the second fin. A portion of the well region positioned between the first spacer and the second spacer is removed to define a trench. A liner layer is formed in the trench, and a conductive line is formed in the trench over the liner layer. The conductive line conductively contacts the well region.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11171212
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee