Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
  • Patent number: 10819325
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10811423
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
  • Patent number: 10804211
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Patent number: 10803967
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10804895
    Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Patent number: 10797078
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 10796760
    Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Cheng Chou
  • Patent number: 10790197
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Patent number: 10784872
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10777426
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Patent number: 10777547
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Patent number: 10763253
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10763258
    Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10756083
    Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10756094
    Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
  • Patent number: 10756192
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Kai-Yu Cheng
  • Patent number: 10748895
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Shih-Chang Liu, Ming Chyi Liu
  • Patent number: 10739673
    Abstract: Embodiments provided herein provide methods for preparing patterned neutral layers using photolithography, and structures prepared using the same. A method of preparing a structure may include disposing a film over a surface of a substrate, and removing plurality of elongated trenches from the film so as to define a plurality of spaced lines. A neutral layer may be disposed over the outer surface of each line, and may include a neutral group attached to the outer surface of that line via a covalent bond or a hydrogen bond. The surface of the substrate between the lines may be substantially free of the neutral layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuan-Hsin Lo, Ching-Yu Chang
  • Patent number: 10734503
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu