Patents Assigned to Taiwan Semiconductor Manufacturing Company, Limited
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Patent number: 11970387Abstract: A micro-electro mechanical system (MEMS) device includes a MEMS substrate, at least one movable element laterally confined within a matrix layer that overlies the MEMS substrate, and a cap substrate bonded to the matrix layer through bonding material portions. A first movable element selected from the at least one movable element is located inside a first chamber that is laterally bounded by the matrix layer and vertically bounded by a first capping surface that overlies the first movable element. The first capping surface includes an array of downward-protruding bumps including respective portions of a dielectric material layer. Each of the downward-protruding bumps has a vertical cross-sectional profile of an inverted hillock. The MEMS device can include, for example, an accelerometer.Type: GrantFiled: March 21, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-wen Cheng, Chi-Hang Chin, Kuei-Sung Chang
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Patent number: 11967582Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.Type: GrantFiled: April 24, 2023Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11968840Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.Type: GrantFiled: November 10, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11961761Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: GrantFiled: March 15, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
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Patent number: 11962240Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.Type: GrantFiled: April 7, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu
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Patent number: 11955405Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.Type: GrantFiled: January 17, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jen Yu Wang, Chung-Jung Wu, Sheng-Tsung Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
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Patent number: 11955561Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.Type: GrantFiled: July 22, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wu-Wei Tsai, Hai-Ching Chen
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Patent number: 11956940Abstract: A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.Type: GrantFiled: January 29, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Gerben Doornbos, Marcus Johannes Henricus Van Dal
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Patent number: 11948628Abstract: Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.Type: GrantFiled: July 28, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Shih-Lien Linus Lu
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Patent number: 11950518Abstract: A phase-change memory device and method of manufacturing the same, the memory device including: a substrate; a bottom electrode disposed over the substrate; a top electrode disposed over the bottom electrode; and a phase-change layer disposed between the top and bottom electrodes. The phase change layer includes a chalcogenide Ge—Sb—Te (GST) material that includes at least 30 at % Ge and that is doped with a dopant including N, Si, Sc, Ga, C, or any combination thereof.Type: GrantFiled: May 27, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Jau-Yi Wu
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Patent number: 11947713Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-En Lee, Shih-Lien Linus Lu
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Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Patent number: 11942146Abstract: Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.Type: GrantFiled: February 13, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Win-San Khwa, Kerem Akarvardar, Yu-Sheng Chen
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Patent number: 11942147Abstract: A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconducting metal oxide layer containing a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on a surface of the channel region, and a gate electrode located on the hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least 90%, and may include hydrogen atoms at an atomic percentage in a range from 0.001% to 10%. Hydrogen atoms may be reversibly impregnated into a respective semiconducting metal oxide layer to change resistivity and to encode a memory bit.Type: GrantFiled: July 25, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Marcus Johannes Henricus Van Dal, Gerben Doornbos, Georgios Vellianitis, Blandine Duriez, Mauricio Manfrini
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Patent number: 11943908Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.Type: GrantFiled: November 9, 2020Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Feng-Ming Chang, Kuo-Hsiu Hsu
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Patent number: 11943933Abstract: A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.Type: GrantFiled: January 17, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Bo-Feng Young, Mauricio Manfrini, Sai-Hooi Yeong, Han-Jong Chia, Yu-Ming Lin
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Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
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Patent number: 11935935Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.Type: GrantFiled: November 11, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
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Patent number: 11929273Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.Type: GrantFiled: July 27, 2020Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tsung-Sheng Kuo, Chih-Hung Huang, Guan-Wei Huang, Ping-Yung Yen, Hsuan Lee, Jiun-Rong Pai
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Patent number: 11929436Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.Type: GrantFiled: September 7, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Neil Murray, Hung-Wei Li, Mauricio Manfrini