Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer.

Abstract: The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.

Abstract: The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.

Abstract: A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening.

Abstract: The present disclosure provides a method and apparatus for cleaning a semiconductor wafer. In an embodiment of the method, a single wafer cleaning apparatus is provided and a wafer is positioned in the apparatus. A first chemical spray is dispensed onto a front surface of the wafer. A back surface of the wafer is cleaned while dispensing the first chemical spray. The cleaning of the back surface may include a brush and spray of cleaning fluids. An apparatus operable to clean the front surface and the back surface of a single semiconductor wafer is also described.

Abstract: The present disclosure provides a method including providing a chamber having a first inlet and a second inlet. A solution of a de-ionized (DI) water and an acid (e.g., a dilute acid) is provided to the chamber via the first inlet. A carrier gas (e.g., N2) is provided to the chamber via the second inlet. The solution and the carrier gas are in the chamber and then from the chamber onto a single semiconductor wafer. In an embodiment, the solution includes a dilute HCl and DI water.

Abstract: A chemical mechanical polishing (CMP) apparatus is provided that includes a conditioning disc for conditioning a polishing pad of the CMP apparatus. The conditioning disc includes a plurality of portions of subsystem discs. The portions may be regions of the disc that are concentric. Each portion of the disc is operable to rotate at a different angular velocity. In some embodiments, a different applied loading is provided to each of the portions of the disc in addition to or in lieu of the different angular velocities.

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract: A method includes providing a wafer and providing a first spray bar spaced a distance from the wafer. A first spray is dispensed from the first spray bar onto a first portion (e.g., half) of the wafer. Thereafter, the wafer is rotated. A second spray is dispensed from the first spray bar onto a second portion (e.g., half) of the rotated wafer. In embodiments, a plurality of spray bars are positioned above the wafer. One or more of the spray bars may be tunable in separation distance and/or angle of dispensing.

Abstract: The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.

Abstract: A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided.

Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).

Abstract: A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Abstract: A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.

Abstract: A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.

Abstract: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.

Abstract: An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO2), followed by a second rinse the semiconductor substrate with DI water and CO2. The first rinse has a first resistivity; the second rinse has a second resistivity lower than the first resistivity.

Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.