Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract: The present disclosure describes a method of forming a pattern by an electron beam lithography system. The method includes receiving an integrated circuit (IC) design layout data having a polygon and a forbidden pattern, modifying the polygon and the forbidden pattern using an electron proximity correction (EPC) technique, stripping the modified polygon into subfields, converting the stripped polygon to an electron beam writer format data, and writing the electron beam writer formatted polygon onto a substrate by an electron beam writer. Stripping the modified polygon includes finding the modified forbidden pattern as a reference layer, and stitching the modified polygon to avoid stitching the modified forbidden pattern.

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Abstract: A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.

Abstract: An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens.

Abstract: The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

Abstract: A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

Abstract: The present disclosure provides a micro device. The device has a micro-electro-mechanical systems (MEMS) movable structure, a plurality of metal loops over the MEMS movable structure, a piezoelectric element over the MEMS movable structure, and a magnet disposed over the plurality of metal loops. The MEMS movable structure, the plurality of metal loops, and the piezoelectric element are encapsulated.

Abstract: The present disclosure provides a chemical mechanical polishing (CMP) system. The CMP system includes a pad designed for wafer polishing, a motor driver coupled with the pad and designed to drive the pad during the wafer polishing, and a controller coupled with the motor driver and designed to control the motor driver. The CMP system further includes an in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller.

Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.

Abstract: A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.