Abstract: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract: A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

Abstract: An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract: Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.

Abstract: A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.

Abstract: The present disclosure provides a method for fabricating a semiconductor device using a track pipeline system. The method includes storing a plurality of chemicals in a plurality of storage units of the system, wherein each storage unit is operable to store one of the chemicals, mixing the chemicals into a mixture, and dispensing the mixture onto a wafer using a nozzle of the system.

Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.

Abstract: An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: A method for photoresist characterization includes forming a photoresist on a supportive structure; and characterizing the photoresist using a metrology tool selected from the group consisting of a transmission electron microscope (TEM), a scanning electron microscope (SEM), an atomic force microscope (AFM), a small angle X-ray scattering (SAXS) and a laser diffraction particle analyzer.

Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

Abstract: A system, method, apparatus, and computer-readable medium for generating a code for a semiconductor manufacturing system are provided. A first code segment is derived from a customer code uniquely associated with a customer. At least one additional code segment is derived from at least one attribute selected for a semiconductor product ordered by the customer. A configure-to-service code is generated in a service guide system from the first code segment and the at least one additional code segment.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Abstract: A method and a system are provided for calibrating metrological tools used to measure features of a semiconductor device. A critical dimension (CD) ruler defines a known pitch plus a pitch offset. A photoresist layer is measured to determine a measured pitch whereupon the measured pitch is compared to the known pitch. From the comparison, appropriate calibration steps can be taken to reduce the difference between the known pitch and the measured pitch.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.

Abstract: An optimized optical proximity correction modeling method comprises receiving a selection of a regression method, displaying regression parameters, receiving values for the displayed regression parameters, receiving a selection of an optimization method, displaying optimization parameters, receiving values for the displayed optimization parameters, and generating an optimized optical proximity correction output.

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than ?1.4 volts.

Abstract: A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({Fj}) and exposure dose ({Ek}) for each of the first plurality of substrates to form a plurality of perturbed wafers. A measuring means is provided for measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. An averaging means is provided for averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map. A second measuring means is provided for measuring a sidewall angle of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers.