Abstract: Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor substrate intersect is disclosed. In one embodiment, the junction includes a portion of at least one current providing electrical interconnect having a length parallel to a longitudinal axis thereof and configured to provide a flow of electrical current. In addition, the junction includes a portion of at least one current receiving electrical interconnect having a length parallel to a longitudinal axis thereof and configured to intersect with the at least one current providing interconnect at the junction in order to receive the flow of electrical current from the at least one current providing interconnect.

Abstract: Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, that is fabricated in substantially the same process steps as a storage capacitor of the volatile memory region. The reduction of process steps allow mixed memory to be fabricated in a cost effective manner.

Abstract: A data filter for filtering process data to a statistical control model is provided to enhance the performance of the control model. The data filter selects a set of template data from a set of statistical process data. A set of grids is formed comprising the set of template data and a set of sample data and an absolute distance is calculated between each point of a grid in the set of grids and a minimum accumulated distance of a point of the grid is calculated using the absolute distance. A global optimal path is identified based on the minimum accumulated distance of the point, and a set of sample data is remapped to form a set of warped data based on the global optimal path and the set of reference data.

Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.

Abstract: A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.

Abstract: A method of manufacturing a microelectronic device, including performing a first inspection of a device feature during an intermediate stage of manufacture, cleaning the device feature after the first inspection, and performing a second inspection of the device feature after cleaning the device feature.

Abstract: Described are microlens designs to increase quantum efficiency and improve photonic performance of photosensitive integrated circuit device. A photosensitive integrated circuit made up of photodiodes, dielectric layers, metal contact holes, metal layers, and passivation stacks are formed on a semiconductor substrate. Microlenses are then formed over these encapsulating layers, the microlenses comprising non-planar surfaces, in particular a biconvex microlens formed above the photodiodes to direct, deliver, and focus incident light to the photodiodes for increased quantum efficiency and improved photonic performance. Color filters are then formed over the microlenses and the photodiodes so as to filter specific wavelengths of light.

Abstract: An integrated circuit chip is provided, which includes a bond pad structure. The bond pad structure includes a bond pad, a first metal plate, and a second metal plate. The first metal plate is located under the bond pad. The first metal plate has a first outer profile area. The second metal plate is located under the first metal plate. A cumulative top view outer profile area of the first metal plate and the second metal plate is larger than the first outer profile area of the first metal plate. The second metal plate may have a second outer profile area that is substantially equal to or larger than the first outer profile area. A first vertical axis may extend through a centroid of the first metal plate, and a centroid of the second metal plate may be laterally offset relative to the first vertical axis.

Abstract: A method for creating a hole in a semiconductor wafer includes forming a hard mask over a dielectric layer, the hard mask including a solid portion and a first opening. A patterning layer is provided over the hard mask, the patterning layer including second and third openings. The second opening of the patterning layer aligns with the first opening of the hard mask and the third opening of the patterning layer aligns with the solid portion of the hard mask. The hole is created in the dielectric layer using the second opening of the patterning layer and the first opening of the hard mask.

Abstract: Disclosed herein are IC package devices and related methods of manufacturing. In one embodiment, an package device includes first and second package substrates, and a first IC chip having at least one coupling structure formed on its active region for electrically coupling the first chip to the first substrate. The IC package also includes a second IC chip having at least one coupling structure formed on its active region for electrically coupling the second chip to the second substrate. The IC package also includes a heat spreader configured to disperse heat from the first and second chips, where the heat spreader has a first surface coupled to a backside of the first chip, and a second surface that coupled to a backside of the second chip. Thus, the backsides of the two chips are oriented towards each other. The internal heat spreader also provide support across the IC package to prevent warpage, and thus maintain coplanarity of the IC package.

Abstract: Described is a metal fuse in a semiconductor device that can be readily blown up without compromising device reliability, as well as methods of manufacturing thereof. In one embodiment, a metal fuse structure according to the disclosed principles comprises a semiconductor substrate, and an interconnect layers located on the semiconductor substrate, where the interconnect layer has metal contacts formed through the interconnect layer. In addition, the structure includes a metal fuse formed over the interconnect layer and in electrical contact with the metal contacts. Furthermore, the structure includes a polymeric coating formed over the metal fuse and the interconnect layer, where the polymeric coating is selected to allow radiation to pass therethrough.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A method includes introducing an acid solution having ethanol and an acid to a substrate and cleaning the substrate using the acid solution; applying an ultrasonic wave to the acid solution substantially during the cleaning of the substrate; and performing a fine cleaning of the substrate after the cleaning of substrate with the acid solution.

Abstract: A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.

Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

Abstract: The present disclosure provides an immersion lithography system. The system includes: an imaging lens having a front surface, a substrate stage positioned underlying the front surface of the imaging lens, and an immersion fluid retaining structure configured to hold a first fluid at least partially filling a space between the front surface and a substrate on the substrate stage. The immersion fluid retaining structure further comprises at least one of: a first inlet positioned proximate the imaging lens and coupled to a vacuum pump system, the first inlet operable to provide the first fluid to the space between the front surface and the substrate, and a second inlet positioned proximate the imaging lens and operable to provide a second fluid on the substrate.

Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

Abstract: Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

Abstract: A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.