Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

Abstract: The present disclosure provides a method for removing particles. The method includes: receiving a pellicle including a pellicle membrane, wherein a particle is disposed on the pellicle membrane; passing a light beam through an object lens, wherein the light beam is focused on a focal region in front of the pellicle membrane by the object lens, and the particle is attracted to be trapped at the focal region; and removing the particle from the pellicle membrane at the focal region.

Abstract: In some aspects of the present disclosure, a circuit in a first power domain is disclosed. In some aspects, the circuit in a first power domain includes a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain. In some aspects, the circuit in a first power domain includes a feedback loop coupled to the first enable-controlled logic gate, the feedback loop including a first inverter and a second enable-controlled logic gate coupled to the first inverter. In some aspects, the circuit in a first power domain includes a second inverter coupled to the feedback loop.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first dielectric layer over a substrate. A first conductive structure overlies the first dielectric layer. A data storage structure is disposed between the first dielectric layer and the first conductive structure. The data storage structure comprises a data storage layer and a grid structure. The grid structure comprises a plurality of opposing sidewalls spaced across a width of the first conductive structure. The data storage layer is disposed along the plurality of opposing sidewalls. The data storage layer comprises a first material and the grid structure comprises a second material different from the first material.

Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Abstract: An exemplary work press assembly for a test handler includes a presser and a guide frame. The presser is configured to secure a device under test (DUT) and press the DUT into a socket for testing. The guide frame is configured to receive guide pins of the socket. The presser extends through an opening of the guide frame, and the guide frame is sandwiched between a first presser portion and a second presser portion. The presser is formed of a first material having a first coefficient of thermal expansion (CTE), and the guide frame is formed from a second material having a second CTE that is less than the first CTE. In some embodiments, a thermal insulation layer(s) separates the presser from the guide frame. In some embodiments, a spacing between sidewalls of the presser and sidewalls of the guide frame is configured to accommodate thermal expansion of the presser.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A method of controlling a wafer stage includes moving the wafer stage to position an immersion hood over a first sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a second sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor. The method further includes moving the wafer stage to define a routing track over the first particle capture area. The method further includes moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.

Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method includes forming a first conductive structure over a substrate and forming a second conductive structure through a dielectric layer over the first conductive structure. The method further includes partially removing the dielectric layer to reduce a thickness of the dielectric layer along a first direction and forming a third conductive structure over the second conductive structure. In addition, a first portion of the third conductive structure is within a projection area of the second conductive structure along the first direction, and a second portion of the third conductive structure is outside the projection area of the second conductive structure along the first direction, and a first bottom surface of the first portion is spaced apart from a second bottom surface of the second portion by a distance along the first direction.

Abstract: A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: An integrated circuit (IC) manufacturing method includes: forming, in a device region of the semiconductor wafer, fins of fin field-effect transistors (finFETs) of the IC; forming, in a seal ring region surrounding the device region, at least one seal ring comprising fins encircling the device region and a monitoring pattern comprising fins encircling the device region; and forming, in the device region, gates of the finFETs of the IC. Polysilicon structures are formed on the fins of the monitoring pattern in a connecting region of the monitoring pattern. An epitaxial material is grown on the fins of the monitoring pattern between the polysilicon structures by a combination of epitaxial growth upward from the fins and epitaxial growth inward from the polysilicon structures. At least one electrical contact is formed that electrically contacts the epitaxial material.

Abstract: A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Abstract: A method includes conducting an electromigration (EM) check process on a schematic design, conducting a mitigating process to mitigate one or more electromigration violations identified during conducting the EM check process, and generating a layout design of the schematic design after at least one iteration of a design process including the EM check process and the mitigating process. The EM check process includes selecting at least some circuits in the schematic design as selected circuits for electromigration check, and checking electromigration compliance in the selected circuits. The mitigating process includes one of modifying some circuit layout of the selected circuits, modifying the schematic design, or modifying both the schematic design and some circuit layout of the selected circuits.