Patents Assigned to Taiwan Semiconductor Manufacturing Company
  • Semiconductor device and method of manufacture
    Patent number: 11328971
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Write driver boost circuit for memory cells
    Patent number: 11328762
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • High voltage device with gate extensions
    Patent number: 11329128
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Integrated circuit including trench capacitor
    Patent number: 11329125
    Abstract: A capacitor comprises at least one primary trench in a substrate, extending in a first direction, and at least one secondary trench in the substrate, extending in a second direction different from the first direction. The capacitor further comprises a first dielectric material separating the substrate from the first capacitor plate of a plurality of capacitor plates, and a second dielectric material separating the first capacitor plate from a second capacitor plate of the plurality of capacitor plates, wherein the first dielectric material, the second dielectric material, the first capacitor plate and the second capacitor plate are at least partially within the at least one primary trench and the at least one secondary trench in the substrate.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Feng Kuo, Chung-Chuan Tseng, Chia-Ping Lai
  • Semiconductor device
    Patent number: 11328975
    Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Semiconductor device with reduced trap defect and method of forming the same
    Patent number: 11329139
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yu-Ming Lin, Clement Hsingjen Wann
  • Wafer level image sensor package
    Patent number: 11329083
    Abstract: An image sensor package is provided. The image sensor package comprises a package substrate, and an image sensor chip arranged over the package substrate. The integrated circuit device further comprises a protection layer overlying the image sensor chip having a planar top surface and a bottom surface lining and contacting structures under the protection layer, and an on-wafer shield structure spaced around a periphery of the image sensor chip. The height of the image sensor package can be reduced since a discrete cover glass or an infrared filter and corresponding intervening materials are no longer needed since being replaced by the build in protection layer. The size of the image sensor package can be reduced since a discrete light shield and corresponding intervening materials are no longer needed since being replaced by the build in on wafer light shield structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Interconnect structure and method
    Patent number: 11328952
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
    Patent number: 11329022
    Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Yen-Ping Wang
  • Radio frequency switch circuit
    Patent number: 11329647
    Abstract: In a communication system, a communication terminal device transmits and receives RF signals frequently. Subsequent to an antenna of the communication terminal device, the communication terminal device includes a radio frequency switch (also referred to as transmit/receive (T/R) switch) that switches between two states at a high frequency, where one state is for receiving RF signal and other state for transmitting RF signal. In the exemplary embodiments of the disclosure, a complementary metal-oxide-semiconductor (CMOS) switch is provided, where the CMOS switch is deigned to have a high reliability by coupling a body of a transistor of the CMOS switch to a bias voltage through a switch, where the insertion loss and isolation are improved for the operation of the CMOS switch.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Garming Liang, En-Hsiang Yeh
  • Method for manufacturing semiconductor package for warpage control
    Patent number: 11329008
    Abstract: A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Shien Chen, Ming-Da Cheng, Ming-Chih Yew, Yu-Tse Su
  • Memory device and methods for programming and reading memory device
    Patent number: 11327860
    Abstract: A memory device and methods for programming and reading a memory device are provided. The memory device includes a memory array and a memory controller. The memory array includes a plurality of one-time programmable (OTP) cells, in which the OTP cells comprises a plurality of data cells for storing data, a plurality of supplementary cells in parallel to the data cells, and one or more redundant cells for each of a plurality of sets of the data cells. The memory controller is configured to program the data cells. The memory controller verifies and records a state of each data cell in a set of the data cells in the corresponding supplementary cell after the programming, and stores the data to be programmed to the data cell using the one or more redundant cells reserved for the set of the data cells when the data cell is verified as failed.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang
  • MEMORY WITH WRITE ASSIST SCHEME
    Publication number: 20220139450
    Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen
  • OPTICAL MODULATOR AND PACKAGE
    Publication number: 20220137440
    Abstract: An optical modulator includes a dielectric layer and a waveguide. The waveguide is disposed on the dielectric layer. The waveguide includes an electrical coupling portion, a slab portion, and an optical coupling portion. The slab portion is directly in contact with both of the electrical coupling portion and the optical coupling portion. The slab portion has a first sub-portion and a second sub-portion connected to the first sub-portion. A top surface of the electrical coupling portion, a top surface of the first sub-portion, and a top surface of the second sub-portion are located at different level heights.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng-Wei Kuo, Huan-Neng Chen, Min-Hsiang Hsu
  • PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220139807
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220139882
    Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220140197
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
  • INTERCONNECT STRUCTURE
    Publication number: 20220139834
    Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Kuan LEE, Cheng-Chin LEE, Hsin-Yen HUANG, Hai-Ching CHEN, Shau-Lin SHUE
  • TESTING APPARATUS
    Publication number: 20220136724
    Abstract: A testing apparatus including a base and a preheating unit arranged on the base is provided. The preheating unit includes a gas generator, a blocking mechanism and a heating device. The gas generator is configured to discharge air toward the base to form an air wall. The blocking mechanism is located above the air wall and forms a heat preservation space with the air wall. The heating device is arranged in the heat preservation space.
    Type: Application
    Filed: December 10, 2020
    Publication date: May 5, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng
  • SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT
    Publication number: 20220140065
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an adhesive element between the magnetic element and the substrate. The adhesive element extends exceeding opposite edges of the magnetic element. The semiconductor device structure further includes an isolation element extending exceeding the opposite edges of the magnetic element. The isolation element partially covers a top surface of the magnetic element. In addition, the semiconductor device structure includes a conductive line over the isolation element.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chien-Chih KUO, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN