Abstract: A semiconductor structure and method for fabricating a semiconductor structure includes using two separate oxide layers to improve device reliability. A first oxide layer is formed adjacent a fin (e.g. a fin of a fin field-effect transistor (FinFET) device), a dummy gate is formed adjacent the first oxide layer, the dummy gate is removed, and a second oxide layer is then formed adjacent the first oxide layer. The use of the second oxide layer can improve device reliability by covering any damage that may be inflicted on the first oxide layer when the dummy gate is removed.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Abstract: A method of manufacturing a semiconductor device includes detecting, using a sensor, liquid spin on glass (SOG) outside of a dispenser nozzle in an abnormal length relative to the dispenser nozzle. The method further includes adjusting, using a controller, a suck back (SB) valve to withdraw liquid SOG from the abnormal length. The method further includes comparing a sensed amount of liquid SOG deposited onto the semiconductor wafer from the dispenser nozzle with at least one set operating parameter. The method further includes pausing sensing of a duration of dispensing liquid SOG onto the semiconductor wafer based on the sensed amount of liquid SOG deposited being outside the at least one operating parameter.

Abstract: A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Abstract: A semiconductor device includes a first conductive line extending in a first direction on a front side of a semiconductor wafer, a first power rail extending in the first direction on a back side of the semiconductor wafer, and a first transistor including a first gate structure extending in a second direction perpendicular to the first direction, first and second active regions adjacent to the first gate structure, and a first channel region extending between the first and second active regions through the first gate structure. A first via is positioned between and electrically connects the first active region and the first conductive line, and a second via is positioned between and electrically connects the second active region and the first power rail.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.

Abstract: A method of making a semiconductor device includes manufacturing an ESD cell over a substrate, wherein the ESD cell includes multiple diodes connected in parallel to each other. The method includes manufacturing a conductive pillar electrically connected to the ESD cell of the semiconductor device; manufacturing a through-silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate within a TSV zone having a TSV zone perimeter, and wherein a first end of the TSV is at a same side of the substrate as the ESD cell, and a second end of the TSV is at a different side of the substrate from the ESD cell. The method includes manufacturing an antenna extending parallel to the TSV at a same side of the substrate as the ESD cell; and manufacturing an antenna pad electrically connected to the TSV, the antenna, and the conductive pillar.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: A load port is capable of monitoring various environmental parameters associated with a transport carrier to minimize and/or prevent exposure of the semiconductor substrates therein to increased humidity, increased oxygen, increased vibration, and/or one or more other elevated environmental conditions that might otherwise contaminate the semiconductor substrates, damage the semiconductor substrates, and/or cause processing defects. For example, the load port may monitor the environmental parameters as indicators of a potential blockage of a diffuser of the transport carrier, and a relief valve may be used to divert a gas away from the transport carrier based on a determination that a diffuser blockage has occurred. In this way, the gas may be diverted through the relief valve and away from the transport carrier to prevent increased humidity, contaminants, and/or vibration from contaminating and/or damaging the semiconductor substrates.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: An integrated semiconductor packaging system includes: a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame; a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer; a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.

Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.