Abstract: An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of the SRAM array. Each of the first plurality of functional SRAM cells share a first bit line (BL). The SRAM array further includes a second SRAM mini array having a second plurality of functional SRAM cells in the first column. Each of the second plurality of functional SRAM cells share a second BL independently controlled from the first BL. The SRAM array further includes and a SRAM dummy array between the first SRAM mini array and the second SRAM mini array. The SRAM dummy array includes a plurality of SRAM array abut dummy cells in the first column. A first endpoint of the first BL and a second endpoint of the second BL are disposed in the SRAM dummy array.

Abstract: A method for making a dual-gate oxide field effect transistors is achieved. The method utilizes a patterned thin silicon nitride layer and a single rapid thermal oxidation step to form a thicker gate oxide for memory and peripheral circuits while forming a thin nitrogen rich gate oxide for high-performance logic circuits. After forming STI around the logic and memory call areas and removing any native oxide, a thin CVD silicon nitride layer is deposited. The Si3N4 is patterned to leave portions over the logic device areas. A single rapid thermal oxidation process is performed to grow a thicker gate oxide on the exposed memory areas while concurrently the Si3N4 is slowly converted to a nitrogen-rich oxide and forms a thinner gate oxide on the logic device areas. The thinner nitrogen-rich gate oxide also retards boron diffusion to make more stable devices.