Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: A semiconductor package structure with a heat dissipating stiffener and method of fabricating the same are provided. In one embodiment, the package structure comprises a substrate having a front side and a back side; a semiconductor chip mounted on the front surface of the substrate; a thermally-conductive stiffener mounted over the front surface of the substrate and surrounding the chip, the stiffener having a first portion and a second portion, wherein the first portion is wider than the second portion so as to allow for easy egress of a dispenser into a gap between the chip and the substrate; an underfill layer filled and cured in the gap; and a plurality of solder balls mounted on the back surface of the substrate.