Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A chip package is provided. The chip package includes a semiconductor substrate having an edge and a protective layer surrounding the semiconductor substrate. The chip package also includes a conductive line over the protective layer and the semiconductor substrate. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the edge.

Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.

Abstract: An apparatus and a method for forming alignment marks are disclosed. The method for forming alignment marks is a photolithography-free process and includes the following operations. A laser beam is provided. The laser beam is divided into a plurality of laser beams separated from each other. The plurality of laser beams is shaped into a plurality of patterned beams, so that the plurality of patterned beams is shaped with patterns corresponding to alignment marks. The plurality of patterned beams is projected onto a semiconductor wafer.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer, forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer, placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF, encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions, and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.

Abstract: A memory device includes a dielectric layer, a bottom electrode, an inter-metal dielectric (IMD) layer, a phase change element in the IMD layer, and a top electrode. The bottom electrode is in the dielectric layer. The IMD layer is over first dielectric layer. The phase change element is in the IMD layer. The top electrode is over the phase change element and is separated from the dielectric layer by at least an air gap free of materials of the IMD layer and the phase change element.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.

Abstract: A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof.