Patents Assigned to Taiwan Semiconductor Manufacturing
  • Capping structures in semiconductor devices
    Patent number: 11652152
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Ming-Huan Tsai, Li-Te Lin, Pinyen Lin
  • Field-effect transistor device with gate spacer structure
    Patent number: 11652158
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Processes for reducing leakage and improving adhesion
    Patent number: 11651994
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Decision feedback equalization embedded in slicer
    Patent number: 11652673
    Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Chun Yang, Wen-Hung Huang
  • Through-substrate via formation to enlarge electrochemical plating window
    Patent number: 11652025
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Ming Chyi Liu, Jiech-Fun Lu
  • Semiconductor device and method for forming the same
    Patent number: 11652053
    Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Metrology method
    Patent number: 11652007
    Abstract: A method includes illuminating a wafer by an X-ray, detecting a spatial domain pattern produced when illuminating the wafer by the X-ray, identifying at least one peak from the detected spatial domain pattern, and analyzing the at least one peak to obtain a morphology of a transistor structure of the wafer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Horng Lin, Chi-Ming Yang
  • Image sensor device and methods of forming the same
    Patent number: 11652127
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S. S. Wang
  • Strained nanowire CMOS device and method of forming
    Patent number: 11652141
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Fin-like field effect transistor patterning methods for achieving fin width uniformity
    Patent number: 11652160
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Epitaxy regions with large landing areas for contact plugs
    Patent number: 11652105
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
  • SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20230141093
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20230140896
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 11, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG, Sheng-Chang CHEN
  • NEGATIVE TONE PHOTORESIST FOR EUV LITHOGRAPHY
    Publication number: 20230142787
    Abstract: A negative tone photoresist and method for developing the negative tone photoresist is disclosed. For example, the negative tone photoresist includes a solvent, a dissolution inhibitor, and a polymer. The polymer includes a hydroxyl group. The polymer may be greater than 40 weight per cent of a total weight of the negative tone photoresist.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 11, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Po YANG, Wei-Han LAI, Ching-Yu CHANG
  • SEMICONDUCTOR STRUCTURE WITH DIELECTRIC FIN STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230141523
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first channel structures and second channel structures formed over the substrate. The semiconductor structure also includes a dielectric fin structure formed between the first channel structures and the second channel structures. In addition, the dielectric fin structure includes a core portion and first connecting portions connected to the core portion. The semiconductor structure also includes a gate structure including a first portion. In addition, the first portion of the gate structure is formed around the first channel structures and covers the first connecting portions of the dielectric fin structure.
    Type: Application
    Filed: February 23, 2022
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Lin CHEN, Jung-Chien CHENG, Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG
  • MEMORY DEVICE HAVING RECESSED ACTIVE REGION
    Publication number: 20230143082
    Abstract: A device includes an active region, a select gate, a control gate, a first metal alloy layer, and a second metal alloy layer. The active region has a source region and a drain region. The select gate is over the active region and between the source region and the drain region. The control gate is over the active region and between the source region and the select gate. The first metal alloy layer is in contact with the source region. The second metal alloy layer is in contact with the drain region and higher than a top surface of the control gate.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yong-Sheng HUANG, Ming-Chyi LIU
  • Process Loading Remediation
    Publication number: 20230145694
    Abstract: Analog and logic devices may coexist on a common integrated circuit chip, accommodating features with different pitches, linewidths, and pattern densities. Such differences in design and layout at various layers during manufacturing can cause process loading by contributing different amounts of reactants to surface chemical reactions. Such variation in the balance of chemical reactants can result in disparities in film thicknesses within the chip that can affect device performance. Embodiments of the present disclosure disclose a masking sequence that can alleviate process loading disparities during an undercut etch process adjacent to polysilicon structures.
    Type: Application
    Filed: June 10, 2022
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ling Wu, Ru-Shang Hsiao, I-Shan Huang, Ying Hsin Lu, C.J. Wu
  • SPLIT VALVE AIR CURTAIN
    Publication number: 20230142009
    Abstract: Contamination from outgassing during a deposition process is addressed by a series of equipment enhancements, including throttle valves, a dual air curtain, and a residual gas analysis (RGA) monitor. The dual air curtain can be configured to flow a first gas during wafer processing and a second gas during wafer unloading, to re-direct and capture outgassed species. The dual air curtain and the throttle valves can be programmed in an automated feedback control system that utilizes data from the RGA monitor.
    Type: Application
    Filed: June 9, 2022
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Wei XU, Yin-Bin TSENG, Kai-Shiung HSU, Chun-Sheng WU
  • SEMICONDUCTOR STRUCTURE WITH ISOLATION FEATURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230144099
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230146366
    Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 11, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei SU, Fu-Ting YEN, Ting-Ting CHEN, Teng-Chun TSAI