Patents Assigned to TAIWAN SEMICONDUCTOR MANUGACTURING COMPANY, LTD.
  • OPERATING METHOD OF MEMORY HAVING REDUNDANCY CIRCUITRY
    Publication number: 20140146613
    Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 29, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUGACTURING COMPANY, LTD.
    Inventors: Tien-Chun YANG, Yue-Der CHIH, Shang-Hsuan LIU