Abstract: A circuit carrier and a manufacturing method thereof are provided. The circuit carrier includes at least one flexible structure and a circuit structure. The flexible structure includes a first dielectric layer and a conductive pattern disposed thereon. The circuit structure is disposed on the flexible structure and electrically connected to the conductive pattern. The circuit structure includes a second dielectric layer and a circuit layer. The second dielectric layer is disposed on the flexible structure and has a Young's modulus different from that of the first dielectric layer. The circuit layer is disposed on and extends into the second dielectric layer to be in contact with the conductive pattern of the flexible structure. The flexible structure is interposed in the circuit structure. A portion of the first dielectric layer and a portion of the conductive pattern of the flexible structure are extended out from an edge of the circuit structure.

Abstract: A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.

Abstract: A resistive network include multiple resistive units; each resistive unit is made up of multiple resistive elements, which can be arranged in a parallel configuration. Each of the resistive elements can be programmable (e.g., switched on or off, or set to one of multiple resistance values). Furthermore, a method of analog computing includes configuring multiple resistive elements in each of multiple resistive units and configuring the resistive units into a network. The configuration of the resistive elements can be, for example, arranging them into a parallel combination. The method further includes programming each resistive unit, for example, by switching individual resistive elements into, or out of, the parallel combination.

Abstract: A method includes forming a dielectric layer over a fin structure, forming a dummy gate crossing over the dielectric layer, forming a spacer on a sidewall of the dummy gate, etching the dielectric layer and the fin structure, such that the dielectric layer and the fin structure are recessed from an outer sidewall of the spacer, and etching the fin structure, such that the fin structure is recessed from an end surface of the dielectric layer.

Abstract: The present disclosure describes a chuck-based device and a method for cleaning a semiconductor manufacturing system. The semiconductor manufacturing system can include a chamber with the chuck-based device configured to clean the chamber, a loading port coupled to the chamber and configured to hold one or more wafer storage devices, and a control device configured to control a translational displacement and a rotation of the chuck-based device. The chuck-based device can include a based stage, one or more supporting rods disposed at the base stage and configured to be vertically extendable or retractable, and a padding film disposed on the one or more supporting rods.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

Abstract: A method is disclosed including following operations. A first signal is applied to memory cells in a memory device, to adjust resistance values of the memory cells. After the first signal is applied, a second signal is applied to the memory cells other than the first memory cell, to further adjust the resistance values of the plurality of memory cells other than the first memory cell. After the second signal is applied, data corresponding to the first predetermined resistance value and the second predetermined resistance value is stored in the first memory cell and the second memory cell, respectively. The first signal is configured for controlling a first memory cell in the memory cells to have a first predetermined resistance value. The second signal is configured for controlling a second memory cell in the memory cells to have a second predetermined resistance value.

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

Abstract: The present disclosure describes a system and a method for a ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.

Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.

Abstract: A polish head of a chemical mechanical polishing system is provided. The polish head includes a carrier head, a membrane mounted to the carrier head, an inner retaining ring mounted to the carrier head and surrounding the membrane, an outer retaining ring mounted to the carrier head and surrounding the inner retaining ring, and an image capturing device. The outer retaining ring is spaced apart from the inner retaining ring. The image capturing device is mounted to the carrier head and between the inner retaining ring and the outer retaining ring.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Abstract: An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.

Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.

Abstract: A package structure is provided. The package structure includes an optical component over a substrate, and a reflector disposed over the substrate. The reflector includes a first semiconductor layer over a second semiconductor layer, and a dielectric layer between the first semiconductor layer and the second semiconductor layer. The reflector also includes a metal layer between the second semiconductor layer and the substrate. In addition, the package structure includes a waveguide between the metal layer and the optical component.

Abstract: The present disclosure is directed to a wafer drying method that detects molecular contaminants in a drying gas as a feedback parameter for a multiple wafer drying process. For example, the method includes dispensing, in a wafer drying module, a drying gas over a batch of wafers. Further, the method includes collecting the drying gas from an exhaust of the wafer drying module and determining the concentration of contaminants in the drying gas. The method also includes re-dispensing the drying gas over the batch of wafers if the concentration of contaminants is greater than a baseline value and transferring the batch of wafers out of the wafer drying module if the concentration is equal to or less than the baseline value.

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.