Patents Assigned to Taiwan Semiconductor
  • Semiconductor device having drain side contact through buried oxide
    Patent number: 9431531
    Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Yang Lin, Hsin-Chih Chiang, Ruey-Hsin Liu, Ming-Ta Lei
  • Antenna structures
    Patent number: 9431714
    Abstract: An antenna formed on a semiconductor structure having a substrate with electrical circuits thereon operationally related to the functionality of an antenna and one or more metallic structures formed by a through silicon via, microbump, copper pillar, or redistribution layer proximate to the substrate. The one or more metallic structures form a radiating element of the antenna. Exemplary antennas thus formed can include a slot antenna, a WLAN slot antenna, a planar invented F antenna (PIFA), a spiral antenna, a dipole antenna, a Yagi antenna, a planar dipole antenna, a vertical dipole antenna, a patch antenna, a helical antenna, a loop patch antenna, and combinations thereof.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hsiao-Tsung Yen
  • Resistive random access memory (RRAM) and method of making
    Patent number: 9431604
    Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Liao, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Chih-Yang Chang, Hsia-Wei Chen
  • Plasma-processing apparatus with upper electrode plate and method for performing plasma treatment process
    Patent number: 9431221
    Abstract: A plasma-processing apparatus is provided. The plasma-processing apparatus includes a processing chamber having an upper portion and a lower portion. The upper portion has a gas inlet. The plasma-processing apparatus includes an upper electrode plate disposed in the upper portion. The upper electrode plate has gas holes passing through the upper electrode plate. The plasma-processing apparatus includes a protective layer disposed over inner walls of the gas holes. The protective layer and the upper electrode plate have different materials. The plasma-processing apparatus includes a lower electrode pedestal disposed in the lower portion for supporting a substrate.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Ju Chen, Chih-Ching Cheng, Hsin-Yi Tsai, Xiao-Meng Chen
  • STI recess method to embed NVM memory in HKMG replacement gate technology
    Patent number: 9431413
    Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao
  • Rotary EUV collector
    Patent number: 9429858
    Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
  • Techniques providing high-k dielectric metal gate CMOS
    Patent number: 9431404
    Abstract: A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng
  • Circuit having a non-symmetrical layout
    Patent number: 9431066
    Abstract: A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Huai-Ying Huang, Kian-Long Lim, Ping-Wei Wang
  • Staggered via redistribution layer (RDL) for a package and a method for forming the same
    Patent number: 9431342
    Abstract: An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo
  • Circuit and operating method of PLL
    Patent number: 9432030
    Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Jen Chen, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • System and method for test key characterizing wafer processing state
    Patent number: 9431288
    Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Drive circuit with an external mode-adjusting pin
    Patent number: 9433045
    Abstract: A drive circuit with an external mode-adjusting pin includes an operational mode control circuit and a drive processing circuit. The operational mode control circuit further includes a current mirror circuit, a resistor, a capacitor and a comparator. The first comparator input port receives a reference voltage. The second comparator input port couples the second output port of the current mirror and the capacitor. The current mirror circuit bases on a resistor current to generate a charge current for charging the capacitor. As the charge voltage at the second comparator input port reaches a reference voltage, a trigger signal is outputted to the drive processing circuit for controlling the switches thereof. The external pin is defined to one end of the resistor or the capacitor for varying the resistance or the capacitance respectively to determine the operational mode for the driven circuit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Yueh-Hua Chiang
  • Method of making a gate structure
    Patent number: 9431505
    Abstract: A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Oxide film scheme for RRAM structure
    Patent number: 9431609
    Abstract: The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
  • Memory circuit and cache circuit configuration
    Patent number: 9431064
    Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Method of forming a semiconductor package
    Patent number: 9431367
    Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Memory macro configuration and method
    Patent number: 9431075
    Abstract: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sergiy Romanovskyy
  • Structure and method of photomask with reduction of electron-beam scatterring
    Patent number: 9429835
    Abstract: The present disclosure provides a structure of a photomask. The photomask includes a substrate; and a conductive material layer dispose over the substrate and patterned to include a plurality of openings and a recess structure surrounding the plurality of openings.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Hsin-Chang Lee
  • Method for fabricating a multi-gate device
    Patent number: 9431397
    Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Adjusting sizes of connectors of package components
    Patent number: 9430605
    Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang, Hung-Jui Kuo, Chung-Shi Liu