Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: An AC-DC power converter includes a rectifying unit, an output stage, a controller and a soft-start circuit. The rectifying unit is configured to rectify an AC voltage to a rectified voltage. The output stage is coupled to the rectifying unit and configured to convert the rectified voltage into a DC voltage for a load. The controller is coupled to the output stage and configured to control the output stage. The soft-start circuit is coupled to the rectifying unit to receive the rectified voltage. The soft-start circuit is configured to detect whether the rectified voltage is at or below a predetermined level, and to enable the controller if the rectified voltage is detected to be at or below the predetermined level.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack.

Abstract: The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an address back-to-back counter; assigning each address back-to-back counter an initial value and a pre-defined threshold, wherein the address back-to-back counter is updated according to the activities of back-to-back access to the resource by the channel; and providing each channel a contiguous window setting to define a number of contiguous times for the channel to access the resource; wherein a channel being served is to be served for contiguous times defined by the contiguous window setting of the channel if the address back-to-back counter value of the channel is higher than the pre-defined threshold of the channel.

Abstract: The present disclosure provides one embodiment of a motion sensor structure. The motion sensor structure includes a first substrate having an integrated circuit formed thereon; a second substrate bonded to the first substrate from a first surface, wherein the second substrate includes a motion sensor formed thereon; and a third substrate bonded to a second surface of the second substrate, wherein the third substrate includes a recessed region aligned with the motion sensor.

Abstract: A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.

Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

Abstract: The present invention discloses pre-amplifier with a selectable threshold voltage in a decision feedback equalization circuit to reduce tap weight variation. A decision feedback equalization circuit includes a summer circuit and a pre-amplifier with an offset generator, wherein the pre-amplifier includes a pair of differential amplifiers and each biased by a respective current bias and each having first and second output nodes coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistor, or any other active or passive circuitry for establishing a resistance. The inputs of first differential amplifier are coupled to the summer's output. The inputs of second differential amplifier are coupled to a reference voltage circuit that comprised of a resistive element and a respective current DAC (IDAC).

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.

Abstract: An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound.

Abstract: A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.

Abstract: An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of light-blocking structures is disposed over the second side of the substrate. A passivation layer is coated on top surfaces and sidewalls of each of the light-blocking structures. A plurality of spacers is disposed on portions of the passivation layer coated on the sidewalls of the light-blocking structures.

Abstract: A circuit includes a signal generator, a delay pulse generator and a time-to-current converter. The signal generator is configured to generate a first signal including information on a rise delay and a second signal including information on a fall delay. A delay difference exists between the rise delay and the fall delay. The delay pulse generator is configured to provide an additional delay to one of the first and second signals. The time-to-current converter is configured to extract the delay difference.

Abstract: A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.