Patents Assigned to Taiwan Semiconductor
  • Mechanisms for forming patterns using multiple lithography processes
    Patent number: 9245763
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Bidirectional dual-SCR circuit for ESD protection
    Patent number: 9245878
    Abstract: An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsiang Song, Jam-Wem Lee, Tzu-Heng Chang, Yu-Ying Hsu
  • Semiconductor device and fabricating process for the same
    Patent number: 9245841
    Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
  • Method and layout of an integrated circuit
    Patent number: 9245887
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Anti-reflective layer and method
    Patent number: 9245751
    Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
  • ESD protection for 2.5D/3D integrated circuit systems
    Patent number: 9245852
    Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hui Chen, Fang-Tsun Chu
  • Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing
    Patent number: 9245991
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Opening fill process and structure formed thereby
    Patent number: 9245797
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Pattern density-dependent mismatch modeling flow
    Patent number: 9245073
    Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Shih-Cheng Yang, Chung-Kai Lin, Yung-Chow Peng
  • RRAM cell including V-shaped structure
    Patent number: 9246084
    Abstract: Embodiments of a resistive random access memory (RRAM) cell structure are provided. The RRAM cell structure includes a first electrode over a substrate. The RRAM cell structure also includes a resistance variable layer over the first electrode. The resistance variable layer has a first portion in a V-shape. The RRAM cell structure further includes a second electrode over the resistance variable layer.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hsing-Chih Lin
  • Method and apparatus for low resistance image sensor contact
    Patent number: 9245912
    Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chun-Chieh Chuang, Shuang-Ji Tsai, Jeng-Shyan Lin
  • Method of making a FinFET device
    Patent number: 9245883
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a first gate stack and a second gate stack over different portions of a fin feature formed on a substrate, forming a first dielectric layer in a space between the first and second gat stacks, removing the first gate stack to form a first gate trench, therefore the first gate trench exposes a portion of the fin feature. The method also includes removing the exposed portion of the fin feature and forming an isolation feature in the first gate trench.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Jr-Jung Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Metal pads with openings in integrated circuits
    Patent number: 9245833
    Abstract: A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Yu-Ting Huang
  • Semiconductor structure having interfacial layer and high-k dielectric layer
    Patent number: 9245970
    Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Performance boost by silicon epitaxy
    Patent number: 9245974
    Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Photomask and method for forming the same
    Patent number: 9244341
    Abstract: A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Anthony Yen
  • Integrated circuit for converting a high voltage level to a low voltage level
    Patent number: 9246388
    Abstract: An integrated circuit for converting a high voltage level to a low voltage level comprises a high side driver, a low side driver electrically coupled with the high side driver, a circuit electrically coupled with the high side driver and a first node between the high side driver and the low side driver, and a false signal filter electrically coupled with the circuit. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode. The false signal filter is configured to screen signals that are outside of the tri-state mode.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Chen Chuang, Alan Roth
  • Integrated circuit design system
    Patent number: 9245078
    Abstract: A design system for designing an integrated circuit, and the design system includes a processor and a computer readable medium embodying computer program code. The computer program code includes instructions executable by the processor and configured to cause the processor to: modify a circuit design of the integrated circuit to compensate for an impact of layout parameters of the circuit design; generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit; calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter; and generate a layout design of the modified circuit design of the integrated circuit according to the at least one recommended layout parameter.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mu-Jen Huang, Yu-Sian Jiang, Chien-Wen Chen
  • Switching circuit
    Patent number: 9245594
    Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu
  • Testing system with an isolated switching module
    Patent number: 9244118
    Abstract: In this invention, a test system includes a tester and a switching module for connecting any pin to the tester for testing a device-under-test (DUT), the test system has a rectifying device between the ground of the DUT and the ground of the switching module in order to isolate the DUT from the switching module, thereby blocking unwanted current flowing between the DUT and the switching module to ensure the correctness of the testing. Since the ground of the switching module is not directly connected to the ground of the DUT and the tester, the rectifying device will keep the voltage difference between the ground of the switching module and the DUT in a range between zero and the cut-in voltage of the rectifying device, thereby allowing single-ended signals to be used between the switching module and the tester or the DUT.
    Type: Grant
    Filed: December 30, 2012
    Date of Patent: January 26, 2016
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching-Tsung Chen, Weichung Chen