Abstract: A method includes ejecting a metal droplet from a reservoir of a droplet generator toward a zone of excitation in front of a collector, emitting an excitation laser toward the zone of excitation, such that the metal droplet is heated by the excitation laser to generate extreme ultraviolet (EUV) radiation, halting the emission of the excitation laser, depressurizing the reservoir of the droplet generator, cooling down the droplet generator to a temperature not lower than about 150° C., and refilling the reservoir of the droplet generator with a solid metal material at the temperature not lower than about 150° C.

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high ? etch residue during formation of the logic device structure with HKMG technology.

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.

Abstract: An image sensor includes a substrate, a grid isolation structure, and a color filter. The substrate has a light-sensitive element therein. The grid isolation structure is above the substrate and includes a reflective layer, a first dielectric layer above the reflective layer, and a second dielectric layer above the first dielectric layer. The color filter is above the light-sensitive element and is surrounded by the grid isolation structure.

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

Abstract: A synergistic design method for an integrated circuit (IC) is provided. The synergistic design method includes forming a standard cell library and a non-standard cell library, implementing an IC design process from a high-level behavior specification through a gate-level netlist to a physical layout, and verifying the physical layout to fabricate the IC. Each standard cell of the standard cell library performs a Boolean logic operation. Each non-standard cell of the non-standard cell library performs a complex function beyond the Boolean logic operation. A conversion process is executed for translating a circuit function into a Boolean network to generate the gate-level netlist based on the standard cells of the standard cell library corresponding to the circuit function. A direct mapping is executed on the non-standard cell by skipping the conversion process during the IC design process to generate the gate-level netlist.

Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).

Abstract: A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end and is floating.

Abstract: A semiconductor device includes a circuit board, a semiconductor package, and a contact interface. The semiconductor package is mounted on the circuit board. The semiconductor package includes a plurality of conductive bumps with a first pitch. The contact interface is electrically connected to the circuit board. The contact interface includes a plurality of first contact pads with a second pitch substantially the same as the first pitch. The first contact pads are separated from the conductive bumps.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.

Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.