Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: A method includes following steps. A photoresist-coated substrate is received to an extreme ultraviolet (EUV) tool. An EUV radiation is directed from a radiation source onto the photoresist-coated substrate, wherein the EUV radiation is generated by an excitation laser hitting a plurality of target droplets ejected from a first droplet generator. The first droplet generator is replaced with a second droplet generator at a temperature not lower than about 150° C.

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: A semiconductor structure includes a channel region of a transistor in a semiconductor fin, source and drain regions of the transistor on the semiconductor fin and at opposite sides of the channel region, a gate of the transistor over the channel region, and a first metal structure. The first metal structure is disposed over a first one of the source and drain regions. The first metal structure includes a first portion lower than a top surface of the gate, a second portion higher than the top surface of the gate, and a third portion over the second portion, wherein the second portion is narrower than the first portion, and the third portion is wider than the second portion.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

Abstract: The present disclosure relates to a semiconductor device that includes a first terminal formed on a fin region and having a first spacer. The semiconductor device further includes a second terminal having a hard mask and a second spacer opposing the first spacer. The hard mask and the second spacer are formed using different materials. The semiconductor device also includes a seal layer formed between first and second spacers of the first and second terminals, respectively. The semiconductor device further includes an air gap surrounded by the seal layer, the fin region, and the first and second spacers.

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.

Abstract: The present disclosure relates to an electroplating system including a first contact detection sensor and a second contact detection sensor disposed at a surface of a cone of the electroplating system. The first contact detection sensor detects a first resistance at a first contact between a substrate to be plated by the electroplating system and a first contact pin, the second contact detection sensor detects a second resistance at a second contact between the substrate and a second contact pin. A controller receives the first resistance and the second resistance, and determines the first contact and the second contact are not properly formed when a difference between the first resistance and the second resistance is not within a first predetermined resistance range, or the first resistance or the second resistance is not within a second predetermined resistance range.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and forming a first plurality of protruding fins and a second protruding fin over the isolation regions. The first plurality of protruding fins include an outer fin farthest from the second protruding fin, and an inner fin closest to the second protruding fin. The method further includes etching the first plurality of protruding fins to form first recesses, growing first epitaxy regions from the first recesses, wherein the first epitaxy regions are merged to form a merged epitaxy region, etching the second protruding fin to form a second recess, and growing a second epitaxy region from the second recess. A top surface of the merged epitaxy region is lower on a side facing toward the second epitaxy region than on a side facing away from the second epitaxy region.

Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.

Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.