Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.

Abstract: A method for forming a phase change random access memory (PCRAM) device is provided. The method includes: forming a memory stack over an insulator layer. A first etch process is performed to pattern the memory stack defining a memory cell including a top electrode overlying a dielectric layer. The dielectric layer includes a center region laterally between a first outer region and a second outer region. An etchant used in the first etch process creates a compound in the first and second outer regions, the compound has a first melting point temperature. A first deposition process is performed to form a first sidewall spacer over the memory cell, the first sidewall spacer is in direct contact with outer sidewalls of the memory cell. The first deposition process reaches a first maximum temperature less than the first melting point temperature.

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

Abstract: At least a first reticle is stored in a housing of a stocker. A first gas is delivered to the housing. At least one reticle pod having an additional reticle is delivered into a enclosure within the housing of the stocker. A second gas different from the first gas is delivered to the enclosure. The reticle pod is automatically retrieved from the enclosure. The delivery and retrieval of the reticle pod and delivery of the first gas and the second gas are automatically controlled.

Abstract: A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores substantially perpendicular to a surface of the semiconductor substrate. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.

Abstract: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.

Abstract: A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.

Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

Abstract: A system for sending multimedia information from at least one base station to one or more mobile stations via at least one wireless communication link includes at least one multimedia source for generating the multimedia information. At least one processor is coupled to the multimedia source for generating a number of data streams derived from the multimedia information on a media control access (MAC) layer. At least one data channel modulator is coupled to the processor for mapping the data streams into a number of data packets on a forward packet data channel between the base station and the mobile station, using a physical layer signaling based on a code-division multiple access (CDMA) or orthogonal frequency division modulation (OFDM) technology.

Abstract: A design for chuck rollers and a design for chuck pins for a wafer cleaning and drying system is disclosed. Each of the chuck rollers includes a roller head which ensures proper engagement of a wafer with the chuck rollers for rotation of the wafer during a wafer scrubbing process. Each of the chuck pins is provided with an extending flange or salient to prevent upward movement of and disengagement of the wafer from the chuck pins as the wafer is rotated during a wafer scrubbing and drying process. Each chuck pin may also present a wafer support surface of enhanced surface area for supporting the wafer on the chuck pin.

Abstract: A method for forming a contact plug. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening that exposes a thin layer of native oxide. A first and a second conformal doped polysilicon layer are formed over the opening. The first doped polysilicon layer has a dopant concentration greater than that of the second doped polysilicon layer. A third doped polysilicon layer that also fills the opening is formed over second doped polysilicon layer. Dopant concentration of the third doped polysilicon layer is smaller than the second doped polysilicon layer. Last, the first, the second and the third doped polysilicon layer are annealed.

Abstract: An apparatus and a method for cleaning a polishing pad used in a chemical mechanical polishing apparatus are disclosed. In the apparatus, a plurality of brush means is mounted to the bottom surface of either a conditioning head, a slurry delivery arm, or both for operating in-situ or ex-situ in a chemical mechanical polishing process. Each of the plurality of brush means may be formed of a multiplicity of bristles made of a polymeric material that is acid resistant and base resistant. A suitable material is nylon that has sufficient hardness for efficient cleaning of surface grooves in a top surface of the polishing pad. The present invention novel apparatus is efficient in removing particles from the surface grooves before the particles present a serious scratching hazard or otherwise damaging the wafer surface during a CMP polishing process.