Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.

Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.

Abstract: High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the active area to define a channel region in the substrate between the drain region and the source region, wherein the active area has at least one side extending along a direction perpendicular to the channel direction of the channel region, such that the gate structure without completely covering the extension.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: A design for chuck rollers and a design for chuck pins for a wafer cleaning and drying system is disclosed. Each of the chuck rollers includes a roller head which ensures proper engagement of a wafer with the chuck rollers for rotation of the wafer during a wafer scrubbing process. Each of the chuck pins is provided with an extending flange or salient to prevent upward movement of and disengagement of the wafer from the chuck pins as the wafer is rotated during a wafer scrubbing and drying process. Each chuck pin may also present a wafer support surface of enhanced surface area for supporting the wafer on the chuck pin.