Abstract: A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows.