Patents Assigned to Taiwan University
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Patent number: 10965466Abstract: A method for calculating a number of proof-of-work to measure how much work has been done in one block mining, includes the following steps: using a low hash, wherein the low hash value corresponding to a low nonce is not greater than a predetermined target value; using a high hash, wherein the high hash value corresponding to a high nonce is higher than the same target value; and calculating the number of proof-of-work according to the low hash value and the high hash value. The low hash value is the lowest hash value in one block mining. The high hash value is the highest hash value in the same block mining.Type: GrantFiled: August 3, 2018Date of Patent: March 30, 2021Assignee: National Taiwan UniversityInventor: Chih-Wen Hsueh
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Patent number: 10959679Abstract: In a noncontact self-injection-locked sensor, a self-injection-locked oscillating integrated antenna is designed to radiate a signal to a subject and be injection-locked by a reflect signal reflected from the subject. Owing to the reflect signal is phase-modulated by vital signs of the subject, a demodulator is provided to demodulate an injection-locked signal of the self-injection-locked oscillating integrated antenna to obtain a vital signal of the subject.Type: GrantFiled: November 27, 2018Date of Patent: March 30, 2021Assignees: Sil Radar Technology Inc., National Taiwan University of Science and TechnologyInventors: Chao-Hsiung Tseng, Li-Te Yu, Jyun-Kai Huang, Chih-Lin Chang
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Patent number: 10957784Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.Type: GrantFiled: June 24, 2019Date of Patent: March 23, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
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Patent number: 10958216Abstract: A device is disclosed that includes a semiconductor substrate, a bottom electrode disposed on a first surface of the semiconductor substrate, an insulating layer disposed on a second surface that is opposite to the first surface, of the semiconductor substrate, a current-to-voltage converter, a first electrode and a second electrode that are separate from each other and disposed on the insulating layer. The first electrode is configured to be applied with an input signal, and the second electrode is configured to output an output current signal that is associated with the input signal, the input signal is configured to have a voltage level that is variable, and the output current signal is configured to have a peak current value and a valley current value. The current-to-voltage converter is configured to receive the output current signal to generate an output voltage signal.Type: GrantFiled: August 22, 2019Date of Patent: March 23, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo Hwu, Ting-Hao Hsu
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Patent number: 10957602Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.Type: GrantFiled: December 12, 2019Date of Patent: March 23, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
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Publication number: 20210079026Abstract: A silicon compound, a preparation method thereof, and a lithium battery are provided. The silicon compound is represented by the following Chemical formula 1: (R1)4-n—Si-(L-A)n??[Chemical formula 1] In Chemical formula 1, each substituent is defined the same as in the specification.Type: ApplicationFiled: March 17, 2020Publication date: March 18, 2021Applicant: National Taiwan University of Science and TechnologyInventors: Fu-Ming Wang, Quoc Thai Pham, Alem Gebrelibanos Hailu, Arif Cahyo Imawan
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Publication number: 20210082482Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 10947120Abstract: A production method of low dimensional nano-material comprises steps of: introducing a layered material; adding an intercalating agent into the layered material; and exfoliating the layered material by ball-milling to form the low dimensional material. Mechanochemical approaches for low dimensional nano-material like graphene quantum dots synthesis offer a promise of new reaction pathways, and greener and more efficient syntheses, making them potential approaches for low cost production.Type: GrantFiled: December 17, 2018Date of Patent: March 16, 2021Assignee: National Taiwan University of Science and TechnologyInventors: Wei-Hung Chiang, Hao-Hsuan Chien
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Patent number: 10940438Abstract: The present invention provides an omniphobic membrane and application thereof. The omniphobic membrane comprises a porous substrate which has a pore size between 0.4 and 2 ?m, a top coat, and an interface layer between the porous substrate and the top coat, and the omniphobic membrane has a carbon/silicon ratio between 40 and 60, and a hierarchical re-entrant structure. Furthermore, both of a process for fabricating the omniphobic membrane and a method for desalination of a liquid by membrane distillation are provided in the present invention.Type: GrantFiled: November 16, 2018Date of Patent: March 9, 2021Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Kuo-Lun Tung, Allen Huang, Liang-Hsun Chen, Yi-Rui Chen, Chien-Hua Chen, Che-Chen Hsu, Feng-Yu Tsai
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Publication number: 20210066060Abstract: A use of an anthranilic acid derivative as a matrix for a MALDI Mass spectrometry, comprising: preparing a matrix compound represented by the following formula: wherein X is selected from hydrogen and a hydroxyl group, and Y is selected from hydrogen, a methyl group or an acetyl group, provided that when X is hydrogen, Y is hydrogen or an acetyl group, and when X is a hydroxyl group, Y is a methyl group; applying the matrix compound and an analyte onto a sample holder; and analyzing the analyte by the MALDI mass spectrometer.Type: ApplicationFiled: September 3, 2020Publication date: March 4, 2021Applicant: National Taiwan UniversityInventors: Cheng-Chih Hsu, Pi-Tai Chou, Chuping Lee, Penghsuan Huang, Li-En Lin, Chun-Ying Huang, Ta-Chun Lin
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Publication number: 20210057408Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chih-Hsiung HUANG, Chung-En TSAI, Chee-Wee LIU, Kun-Wa KUOK, Yi-Hsiu HSIAO
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Publication number: 20210058034Abstract: A device is disclosed that includes a semiconductor substrate, a bottom electrode disposed on a first surface of the semiconductor substrate, an insulating layer disposed on a second surface that is opposite to the first surface, of the semiconductor substrate, a current-to-voltage converter, a first electrode and a second electrode that are separate from each other and disposed on the insulating layer. The first electrode is configured to be applied with an input signal, and the second electrode is configured to output an output current signal that is associated with the input signal, the input signal is configured to have a voltage level that is variable, and the output current signal is configured to have a peak current value and a valley current value. The current-to-voltage converter is configured to receive the output current signal to generate an output voltage signal.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Ting-Hao HSU
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Publication number: 20210057715Abstract: The disclosure provides a primary battery and an electrode assembly thereof. The electrode assembly includes a separator, a positive electrode, and a negative electrode current collector. The separator has a positive electrode side and a negative electrode side opposite to each other. The positive electrode is located at the positive electrode side of the separator, and the positive electrode includes a positive electrode current collector and a positive electrode material. The negative electrode current collector is located at the negative electrode side of the separator. The electrode assembly does not include a negative electrode material before charging or activation.Type: ApplicationFiled: March 19, 2020Publication date: February 25, 2021Applicant: National Taiwan University of Science and TechnologyInventors: Bing-Joe Hwang, Wei-Nien Su, Chen-Jui Huang, Shi-Kai Jiang
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Publication number: 20210057488Abstract: A memory device includes a transistor and a memory cell. The memory cell includes a bottom electrode, a top electrode, and a dielectric structure. The top electrode is electrically connected to the transistor. The dielectric structure includes a thin portion and a thick portion. The thin portion is sandwiched between the bottom electrode and the top electrode. The thick portion is thicker than the thin portion and between the bottom electrode and the top electrode.Type: ApplicationFiled: August 23, 2019Publication date: February 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Tzu-Hao CHIANG
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Publication number: 20210057524Abstract: A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yen LIN, Kuan-Chao CHEN, Hsuan-An CHEN, Lun-Ming LEE
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Publication number: 20210043538Abstract: A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.Type: ApplicationFiled: October 9, 2020Publication date: February 11, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jhih-Yang YAN, Fang-Liang LU, Chee-Wee LIU
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Patent number: 10912936Abstract: A tube-docking holding device includes a first connector bracket and a second connector bracket. The first connector bracket includes two shells. When the two shells are closed, a first accommodation space is surrounded for fixing a portion of a first connector assembly of a catheter. The second connector bracket includes a base body and a cover body. The base body includes a first inner shell and a first outer shell. The cover body includes a second inner shell and a second outer shell. When the cover body and the base body are closed, the first inner shell and the second inner shell surround and define a second accommodation space for fixing a portion of a second connector assembly of a dialysate tube. An interconnected guiding space is formed between the first inner shell and the first outer shell and between the second inner shell and the second outer shell.Type: GrantFiled: October 1, 2018Date of Patent: February 9, 2021Assignees: National Formosa University, National Taiwan University Hospital Yun-Lin BranchInventors: Sung-An Lin, I-En Lin, Feng-Jung Yang, Hao-Ting Chiang
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Patent number: 10915169Abstract: Correction method and device for an eye-tracker are provided. A non-predetermined scene frame is provided and analyzed to obtain a salient feature information, which is in-turn used to correct an eye-tracking operation. The correction can be done at the initial or during the wearing of an eye-tracker.Type: GrantFiled: March 11, 2019Date of Patent: February 9, 2021Assignee: National Taiwan UniversityInventors: Shao-Yi Chien, Chia-Yang Chang, Shih-Yi Wu
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Patent number: 10895911Abstract: An image operation method and system for obtaining an eye's gazing direction are provided. The method and system employ multiple extraction stages for extracting eye-tracking features. An eye frame is divided into sub-frames, which are then sequentially temporarily stored in a storage unit. Launch features of sub frames are sequentially extracted from the sub frames by a first feature extraction stage, where a data of a former sub-frame is extracted before a data of a latter sub-frame is needed to be stored. Next, the remaining feature extraction stages apply a superposition operation on the launch features to obtain terminal features, which are then computed to obtain an eye's gazing direction.Type: GrantFiled: March 12, 2019Date of Patent: January 19, 2021Assignee: National Taiwan UniversityInventors: Shao-Yi Chien, Yu-Sheng Lin, Po-Jung Chiu
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Patent number: 10895910Abstract: An adaptive eye-tracking calibration method includes generating an eye model acting as a current eye model; calibrating the eye model; comparing real-time pupil data set and pupil data set of the current eye model to obtain a pupil data difference when an event happens; and generating a new eye model if the pupil data difference is greater than a predetermined threshold.Type: GrantFiled: March 11, 2019Date of Patent: January 19, 2021Assignee: National Taiwan UniversityInventors: Shao-Yi Chien, Liang Fang
