Abstract: An automatic addressing technique for flexibly specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability.

Abstract: A structured query language (SQL) grouping and aggregation system and method that incorporates hash-based techniques, several overflow handling strategies and statistics-based process-selection criteria. The method can execute SQL group-by queries on distributed database tables or tables stored locally to the database management system (DBMS) processor executing the grouping method. Hash-based techniques allow groupings and aggregates to be generated on the fly through the use of partial aggregates maintained in primary memory. Where primary memory is limited, groups and aggregates are still generated for as many groups as can be maintained in primary memory, while various overflow procedures are provided for buffering ungrouped data and writing that data to an overflow disk file for later processing. In one overflow procedure, raw data from groups that cannot be aggregated in primary memory are buffered then written to the overflow disk file.

Abstract: A system and a method for implementing remote procedure calls in a distributed computer system provide a base object class from which all distributed objects can be derived. A program extracting all classes derived from the base class provides an inheritance tree to allow down casting from a root class to a base class and to allow passing high level data structure between participants of a remote procedure call. An Unix script provides stub routines for implementing a client-server model communicating processes.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.

Abstract: A method and mechanism for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Abstract: A pulse length indicator, for signaling when the length of a pulse from a cyclic signal source has exceeded a chosen duration, has a ramp signal generator, coupled to the cyclic signal source, which produces a ramp signal. The level of the ramp signal is dependent upon the duration of either of the high and low levels of the cyclic signal. The ramp signal is fed to a level sensitive switch which couples an indicator, typically an LED, to a power source. When the level of the ramp signal is sufficiently long or short, the switch closes to actuate the indicator. The ramp signal generator can be a simple R-C circuit with the signal source being AC or DC coupled to the switch.

Abstract: A method for forming multiple metallization layers on a semiconductor wafer comprises applying insulating polyimide layers between adjacent metallization layers. Vertical interconnect holes are formed through the polyimide insulating layers using a positive photoresist mask. The vertical interconnect holes are etched using a fluorocarbon- or fluorosilicon-oxygen plasma under power and temperature conditions which provide for selectively etching the polyimide relative to the photoresist. By initially forming the plasma etch at high power conditions which reduce the selectivity for the polyimide, the upper portion of the vertical interconnect hole walls may be flared to reduce problems with step metallization. The remaining portion of the plasma etch, however, is performed under conditions which are more highly selective for the polyimide which provides for better dimensional control and eliminates formation of a contaminating layer at the bottom of the vertical interconnect hole.