Abstract: A new process is described for verifying a user and/or authenticating a smart card in an off-line computer environment with limited a priori knowledge on the part of the verifier. This process advantageously uses the computational capability and the physical and logical security characteristics offered by a smart card.

Abstract: A session recovery mechanism that permits the recovery of a session with a minimal delay to a user and with minimal data loss. When the client/server communications protocol process, such as TCP/IP process, issues an error message to a server and a client, the server and the client switch from a server data socket and a client data socket, respectively, to a new server data socket and a new client data socket, respectively. This switchover is achieved by having the client open a listening socket during its initialization process. Using the client listening socket, the client listens for a connection from the server to switch to a new data socket, in case of, for example, error messages from the TCP/IP process.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A communication system transmitting AMI encoded data forces a latent error to occur within a predetermined time duration from an event which generated the latent error. Bit values of original data are selectively inverted to prevent a long sequence of zeros from being transmitted.

Abstract: A method and system for maintaining database integrity utilizes a LOG file organized into slots with the number of slots never exceeding the largest number of concurrent transactions updating the database.

Abstract: An effective connector mechanism is described which allows modules to be easily and reliably connected and disconnected. This connector mechanism includes a coordinated arrangement of guide plates featuring mating guide rails and U-shaped channels along with matched sets of tapered pins with tapered slots as well as a spring biased latching mechanism. When mated together, the rails, U-shaped channels, pins and slots lock the modules into engagement in every direction except the forward direction. To prevent forward disengagement, a spring biased latching assembly is provided. This latching assembly features two symmetrically operating latch handles which are each pivotally connected to a T-shaped pawl. When the latch handle is open, the T-shaped pawl rests at the bottom of a ramped runner cut into the walls one module's U-shaped guide channel.

Abstract: A technique for analyzing test results obtained by applying a binary table and a suite of test scripts to a test subsystem control facility for a distributed systems network. The binary table expresses a proposed set of requirements for a proposed subsystem control facility. The suite of test scripts is prepared from a knowledgebase containing test generation information relating to a predetermined global set of subsystem requirements. The test results are compared with the knowledgebase containing the predetermined set of subsystem requirements, and the relative performance of the proposed set of requirements with the predetermined set of subsystem requirements is graphically displayed or printed. The predetermined set of subsystem requirements includes rules governing the operation of a subject network and a library of permitted commands and object types. The proposed set of requirements includes paired selections of commands and object types from the library.

Abstract: A method for subquery elimination for a relational model database based on the SQL language running a database management system (DBMS) under the TANDEM NONSTOP (tm) operating kernel. A series of seven transformation rules are applied to eliminate nested queries in the SQL language. The method and teachings of the present invention generalizes to all types of nested subqueries in SQL, allowing for more efficient computations, allocation and maintenance of system resources.

Abstract: A method and system for preparing a suite of test scripts for testing a proposed network management application. The proposed network management application, termed a subsystem control facility (SCF), is first defined as a set of requirements with the aid of a developmental tool incorporating a subsystem knowledgebase and a test generation knowledgebase. The subsystem knowledgebase contains the rules governing the operation of a given network and a library of permitted commands, objects, attributes, modifiers and other data. The test generation knowledgebase includes information relating to those commands and objects specific to the proposed subsystem control facility set of requirements. A user interface coupled to the knowledgebases permits the selection of types of tests and specific commands and objects to be tested.

Abstract: A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of arbitration to select one of the inputs for data communication to an output. The first (lower) level of arbitration bases selection upon a round-robin order; the second (higher) arbitration level selects inputs based upon an indication from an input of an undue wait for access to the output over a period of time. Each input is provided a modulo-N counter, and a digital counter. Each time an input contends for access to an output and loses to selection by the output to another input, the modulo-N counter is incremented by an assigned value for that input. When N is exceed without access, the digital counter is incremented. The content of the counter operates to force the high-level arbitration.

Abstract: A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input is kept waiting. Each input is provided an assigned bias value from which is developed the accumulated bias value that is compared with that of other inputs arbitrating for access to an output. The output selects one of the inputs, based upon the comparison, and the accumulated bias value of the selected input is diminished by the sum of the assigned bias values of the inputs participating in the arbitration, but not selected, while the accumulated bias values of the other participants are each increased by their corresponding assigned bias values.

Abstract: A digital system, comprising a plurality of integrated circuits that are designed to be scannable for pseudo-random scan testing. Testing begins and proceeds in normal binary-tree fashion, subjecting the system to a pseudo-random scan test and developing from that test a signature that is compared to a standard signature. If the comparison is unequal, portions of the system are subjected to pseudo-random scan testing, in normal binary-tree fashion, until the integrated circuit level is reached whereat a final mis-compare for the signature developed for a integrated circuit is obtained. Then, each bit position of the scan for such integrated circuit is classified according to the source of data for its primary input, and pseudo-random scan testing conducted to extract signatures for each such classified source. When a bad signature is reached, after comparing to standard signatures, the fault has been isolated to the classified source.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: Multiple processors are connected to form a multiprocessor system having inter-processor communicating capability. Each processor maintains a configuration option register indicating the resources necessary to operate the multiprocessor system. In the event of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. Those processors not receiving a power-fail signal will attempt to reconfigure the multiprocessor system, waiting a reasonable amount of time for the processor receiving the power-fail signal to continue operations. If the processor has not recovered from the power-fail signal after a reasonable amount of time, the other processors check the configuration option register to determine whether that processor is necessary for operation of the multiprocessor system.

Abstract: The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a sequence of software code, and then a first instruction loop is implemented with that software code. The processor is then released from a reset state, and the first instruction loop is executed. This first instruction loop is capable of being executed for an indefinite length of time, and it can execute software instructions on a periodic basis. The first instruction loop is then modified into a second instruction loop. The first and second instruction loops have at least one different instruction. The processor within the system of multiple processors is thus initialized.

Abstract: The present invention is a distributed computer system having a plurality of end user terminals and a plurality of loosely coupled server computers that share no resources with each other. A multiplicity of user application processes are distributed over the server computers. A temporary storage file is stored on a first one of the server computers, for temporarily storing queues of data records. Each user application process responds to execution of a WriteQ TS instruction specifying data to be stored in a specified temporary storage queue by generating and storing at least one TS data record in the temporary storage file representing the specified data. Each TS data record has a primary key indicating the record's position in the specified temporary storage queue. Each TS data record is stored in the same temporary storage file on the first server computer regardless of which server computer executes the WriteQ TS instruction.

Abstract: A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.