Abstract: A dual processor system in which one processor is dedicated to input/output tasks while the other is dedicated to high level language tasks when operating as a 16-bit machine. The processors include a first microprocessor which is an 8-bit machine, and a second microprocessor which is a 16-bit machine. The first processor has a memory associated therewith which may, for example, be a 64K memory while the second processor has a larger capacity memory. The second processor does not access the memory of the first processor, however, the first processor can access a portion of the second processor's memory. Access to the second processor's memory is controlled by an arbitrator that is operated by system software to prevent access conflicts. For boot-up during power-up operation, a boot ROM is used, attached to the 8-bit processor having stored therein a boot strap program that is initially loaded into the 8-bit processor memory.

Abstract: A bandpass filter suitable for use in modem circuitry and other applications which require the filter's center frequency to be switched is disclosed. The filter circuit has the characteristic that although the center frequency is changed the overall gain of the filter remains constant. This characteristic results from using a plurality of filter sections which each have low individual gain and providing compensating gain at the input of the filter. In addition, compensating gain elements are used in each filter section so that when the center frequency of the filter is changed, the gain of each filter stage remains constant.

Abstract: The computer system of this invention has, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. A reset switch is operable by the operator of the computer system to reset the system by forcing the CPU to a known address.

Abstract: The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data.

Abstract: A container with a pivotal closure member and latching means for said closure member is disclosed. The latching means includes a female part defining an entry leading to an enlarged area relative to said entry, and a compressible male part sized and shaped to occupy said enlarged area after being compressed through said entry, the female part being mounted on one of said container and closure member, and the male part being mounted on the other of said container and said closure member.

Abstract: A memory management system for providing memory protection for various programs running in a computer such as a 16-bit multi-tasking computer system. The scheme of the present invention provides address translation so as to provide separation of memory spaces. In this connection, each program in the machine has associated therewith, two numbers including an offset number and a limit number. Each program is written so that its base starting address is at the same predetermined address, preferably zero. The address space for each program is separated in memory by adding the offset number for that program to the base address to provide the physical address number. The program is prevented from accessing any memory area outside of its allotted area by comparing the sum of the offset and processor addresses to the limit number.

Abstract: In a computer system operating under read only memory control and having a keyboard, a video terminal, and a port device in the form of a tape recorder/player, an improved apparatus for alpha-numeric/graphic display in which the outputs of respective character and graphic generators couple to respective first and second shift registers with the shift registers being controlled by first and second gate means in a manner to enable clocking of the first shift register when the type code indicates alpha-numeric display and enabling clocking of the second shift register when the type code indicates graphic display.

Abstract: Electronic circuitry for generation of graphics images on a computer display screen is disclosed which allows graphics capability to be added or retrofitted to computers having standard video display character generation circuitry. The graphics circuitry receives address, data and control signals from the normal computer peripheral bus. Address signals received by the graphics circuitry are interpreted as command signals and, in accordance with the command signals, data present on the computer peripheral data bus is interpreted either as graphics data to be written in a random access graphics memory or as an address location for such data in the memory. The graphics circuitry normally operates asynchronously with respect to the computer under control of the character clock generated by the character generation circuitry.

Abstract: The computer system of this invention has a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data.

Abstract: A microprocessor controlled telephone answering device displays a message number and the date and time received for each recorded message as the message is played back. Other features include a cue function for selecting messages as they are played back. The answering device can automatically rewind back and locate a cued message to replay that selected message. Also, digital function codes can be transmitted over a telephone by a remote control unit to control a large number of answering device functions from a remote location. Additional features include the capability for easily entering a new security code into both the answering device and the remote control unit.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by converting the audio waveform into a square wave and examining the square wave for predetermined pulse patterns. If one pattern is found, the positive-going edge of the waveform is selected as the bit cell boundary. If, on the other hand, another pattern is found, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: An input/output bus structure for a computer system is disclosed in which the computer's central processor is fully protected from "foreign" I/O devices in that all of the incoming and outgoing bus signals are buffered and the buffer stores can be disabled under software control. To attach an input/output device on the input/output bus, certain requirements, both hardware and software, must be met. The input/output bus is enabled by writing a predetermined bit pattern to a preselected output port. In response to the bit pattern, hardware in the input/output port enables the input/output bus tranceivers to receive and send information.

Abstract: A charge-discharge switching circuit for use in a cordless telephone which automatically connects and disconnects the receiver and transmitter circuits from a rechargeable storage battery in the handset in response to the base unit charger signal so that the transmitter and receiver circuits are disconnected from the storage battery when it is being charged by the charger in the base unit of the cordless telephone.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by squaring the audio waveform and measuring two successive time intervals occurring between three successive positive-going transitions and subtracting the resulting measurements. If the calculated difference is less than a predetermined amount, positive-going transitions of the waveform are selected as bit cell boundaries. If, on the other hand, the calculated difference is greater than the predetermined amount, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: An interface circuit is disclosed for connecting a digital computer to a modem or other peripheral circuit through either a standard digital signal (RS232) "port" or an audio-frequency "port" normally used by the computer to store and retrieve information on audio-frequency magnetic tapes. The interface circuit allows the modem to be used economically with a small computer which does not have a standard RS232 "port". In order to allow the modem to connect to the audio-frequency "port" the interface circuitry combines filtered audio signals received by the modem from an associated telephone line with RS232 signals generated by the modem decoding circuitry to produce tone bursts which can be decoded by the computer audio-frequency port. The interface circuitry can accept either RS232 signals or tone bursts from the computer to be transmitted by the modem by automatically adjusting an internal threshold level.

Abstract: A bandpass filter suitable for use in modem circuitry and other applications which require the filter's center frequency to be switched is disclosed. The filter circuit has the characteristic that although the center frequency is changed the overall gain of the filter remains constant. This characteristic results from using a plurality of filter sections which each have low individual gain and providing compensating gain at the input of the filter. In addition, compensating gain elements are used in each filter section so that when the center frequency of the filter is changed, the gain of each filter stage remains constant.

Abstract: A telephone ringer system is disclosed which uses an oscillator circuit to drive a piezoelectric transducer to produce the ring signal.

Abstract: The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data.