Abstract: Embodiments include systems and methods of hardware-assisted assembly of documents. For example, one embodiment comprises a memory configured to store documents and at least one processor configured to identify a template for generating a document. The template defines at least one field having a specified position and length within the document. The processor is further configured to store a copy of the template to the memory so as to initialize the document and to store characters based on data associated with the field to a location of the memory associated with the field. The processor further stores, based at least in part on the text and the length of the field, one or more indicators of at least one portion of the field to be removed from the document. The system further includes a circuit configured to read the document from the memory and remove the portion of the field based on the indicators.

Abstract: A method of processing queries, e.g., XPath expressions, related to an XML document includes generating a plurality of tokens based on the contents of the XML document. At least one query expression is compiled to a first plurality of query nodes defining a tree. A plurality of lookup tables may be configured to relate each of the first plurality of query nodes by a symbol. Each token is processed by looking up the query nodes indexed by a symbol matching the token in one of the plurality of lookup tables, marking each of the related query nodes, and indicating a match if each of the first plurality of query nodes of the at least one query expression is marked. A system for performing the method includes a tokenizer, an expression compiler, and an engine module.

Abstract: A method for reducing the size of a DFA associated with a regular expression separates the functions of locating subexpressions within the DFA and determining if the located subexpressions satisfy a regular expression. For example, the functions of (1) locating subexpressions in a range asserting expression and, (2) determining whether the subexpressions satisfy the range of the range asserting expression are partitioned. In one embodiment, a first component may locate the subexpressions in a data stream using one or more DFAs, while a second component determines if the located subexpressions satisfy the range. In this embodiment, because the DFAs are not configured to determine a relationship between subexpressions, such as a range between subexpressions, the size of the resultant DFA may be significantly reduced.

Abstract: A method of processing queries, e.g., XPath expressions, related to an XML document includes generating a plurality of tokens based on the contents of the XML document. At least one query expression is compiled to a first plurality of query nodes defining a tree. A plurality of lookup tables may be configured to relate each of the first plurality of query nodes by a symbol. Each token is processed by looking up the query nodes indexed by a symbol matching the token in one of the plurality of lookup tables, marking each of the related query nodes, and indicating a match if each of the first plurality of query nodes of the at least one query expression is marked. A system for performing the method includes a tokenizer, an expression compiler, and an engine module.

Abstract: A method for reducing the size of a DFA associated with a regular expression separates the functions of locating subexpressions within the DFA and determining if the located subexpressions satisfy a regular expression. For example, the functions of (1) locating subexpressions in a range asserting expression and, (2) determining whether the subexpressions satisfy the range of the range asserting expression are partitioned. In one embodiment, a first component may locate the subexpressions in a data stream using one or more DFAs, while a second component determines if the located subexpressions satisfy the range. In this embodiment, because the DFAs are not configured to determine a relationship between subexpressions, such as a range between subexpressions, the size of the resultant DFA may be significantly reduced.

Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.

Abstract: Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Abstract: A network node, such as an Ethernet switch, is configured to monitor packet traffic using regular expressions corresponding to Access Control List (ACL) rules. In one embodiment, the regular expressions are expressed in the form of a state machine. In one embodiment, as packets are passed through the network node, an access control module accesses the packets and traverses the state machine according to certain qualification content of the packets in order to determine if respective packets should be permitted to pass through the network switch.

Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.

Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.

Abstract: A system for tokenizing a document, such as, for example, an XML document. A classifier is configured to assign the at least one character to at least one of a plurality of character classes. Each of a plurality of token logic units is configured to concurrently perform a comparison as specified by an instruction. A comparison may comprise comparing the at least one character class to an operand. An execution unit is configured to select an action from the instruction in response to performing the comparisons and to perform the action. A method of tokenizing a document includes assigning at least one character from a document to at least one of a plurality of character classes and concurrently performing a plurality of comparisons. At least one of the plurality of comparisons comprises comparing the assigned character class to the character from the document.

Abstract: A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.