Patents Assigned to Tawiwan Semiconductor Manufacturing Co., Ltd.
  • Etch profile control of interconnect structures
    Patent number: 11195750
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo