Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled for an operation on a set of memory cells in an array, sequentially engaging subsets of memory cells for the operation while keeping the remaining memory cells of the set on hold until all the memory cells of the set have been operated on.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract: Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.