Abstract: In the present telecommunication system, a wired network receives a plurality of voice signals and transmits them. A first communication device is connected to the wired network. The first communication device includes means for receiving the plurality of voice signals, a first storage means for storing the plurality of voice signals, a first playback means for retrieving a portion of the stored plurality of voice signals, and a first control means for controlling the first playback means to transmit the retrieved portion of voice signals. The portion of the stored plurality of voice signals which are retrieved are then placed onto a wireless network which is in communication with a plurality of portable units. Each of the portable units has capability of communicating with the wireless network for receiving the voice signals therefrom, for storing a received voice signal, and for playing back the stored voice signal.

Abstract: In the present telecommunication system, a wired network receives a plurality of electrical signals, such as voice signals and transmits them. A first communication device is connected to the wired network. The first communication device includes means for receiving the plurality of electrical signals, a first storage means for storing the plurality of electrical signals, a first playback means for retrieving a portion of the stored plurality of electrical signals, and a first control means for controlling the first playback means to transmit the retrieved portion of electrical signals. The portion of the stored plurality of electrical signals which are retrieved are then placed onto a wireless network which is in communication with a plurality of portable units. Each of the portable units has capability of communicating with the wireless network for receiving the electrical signals therefrom.

Abstract: The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.

Abstract: In a digital wireless communication system operating between a first unit and a second unit, the first unit transmits a digitally encoded RF signal at a first frequency in a plurality of a non-contiguous time slots to the second unit. The second unit receives the digitally encoded RF signals. The received RF digitally encoded signal is converted to an intermediate frequency (IF). An A to D converter samples the received IF digitally encoded signals and generates a plurality of discrete binary symbols during one of the plurality of non-contiguous time slots. A phase error signal is generated for each one of the plurality of discrete binary symbols. A frequency error signal is generated for the subsequent symbol in accordance with .DELTA.f(n+1)=.DELTA.f(n)+g.sub.1 (.crclbar.(n)-.crclbar.(n)). The conversion of the RF signal to intermediate frequency is controlled in response to the frequency error signal.

Abstract: A protocol for wireless local area network communication between a base stationary unit and a plurality of wireless terminals is disclosed. The main features of this protocol is based upon channel reservation requests by active wireless terminals. Contention is resolved and authorization is granted with data message signals transmitted by the authorized wireless terminal either immediately for asynchronous service or periodically for a time-based service. The system further provides for the base stationary unit to query the receipt of the data message signal by the wireless terminal authorized to receive the transmission. If no response signal is received, then the base stationary unit would authorize for itself transmission of the data message to relay it, either "over the air" or via wired connection to another base stationary unit in another data cell.

Abstract: A modularly configured networked document processing system has a plurality of computers communicating over a local area network. The system has fax servers and scanners to convert documents into image signals, work stations to recognize character signals from the image signals, to process the character signals, and to display the unintelligible processed character signals for user intervention. In addition, the system has a gateway for communication to a mainframe computer.

Abstract: A diversity combiner for a digital receiver receives a plurality of complex baseband signals (S.sub.1 (t), S.sub.2 (t)) each having an associated receive signal strength-intensity signal (RSSI.sub.1, RSSI.sub.2). The combiner differentially detects each of the complex baseband signals (S.sub.1 (t), S.sub.2 (t)) to produce a plurality of differential signals (RX.sub.1 (t), RX.sub.2 (t)) in accordance with:RX.sub.1 (t)=S.sub.1 (t).multidot.S.sub.1 *(t-T), andRX.sub.2 (t)=S.sub.2 (t).multidot.S.sub.2 *(t-T)where S.sub.x * is the complex conjugate of S.sub.x and T is a symbol delay. The differential signals (RX.sub.1 (t), RX.sub.2 (t) ) are processed to produce a selected differential signal R(t). The selected differential signal R(t) is converted to produce a plurality of converted signals D.sub.1 (t) and D.sub.2 (t) in accordance with:D.sub.1 (t)=R(t).multidot.e.sup.-j2.pi.fstD.sub.2 (t)=R(t).multidot.e.sup.+j2.pi.fstThe converted signals D.sub.1 (t) and D.sub.2 (t) are further processed to produce timing (.

Abstract: A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.