Abstract: A wideband low noise amplifier (LNA) includes a correction circuit added to compensate for third order intermodulations. A version of the third order nonlinearities created in the main LNA is created in an auxiliary, low power scaled version of the LNA, phased appropriately using a current mirror, and subtracted from the main signal path by summing, thus providing a cancellation of the third order intermodulation (IM) terms in the main signal path leaving a signal remaining which is significantly more spectrally pure than the signal produced by the LNA before correction.

Abstract: A self-tuning filter that is well suited for use as a output digital filter in a direct conversion delta-sigma transmitter is constructed as a high pass finite impulse response filter having a cutoff frequency of twice the desired carrier frequency. The filter is clocked using the same clock as used for the commutatation within the transmitter. The aliasing effect of the digital filter produces a passband centered around the carrier frequency which allows the information contained in the spectrum around the passband to be transmitted, while effectively filtering out the quantization noise produced by the commutation. When the commutator clock frequency is changed in order to change the carrier frequency, the passband automatically moves to track the new carrier frequency. The output filter may be constructed using series connected flip-flops with analog taps and an analog summer connected to respective Q and Q outputs, thereby producing an analog output.

Abstract: A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

Abstract: A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application includes a plurality of differential comparators and a plurality of offset voltage generators. Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage.