Patents Assigned to Technologies AG
  • Self-aligned dual damascene etch using a polymer
    Patent number: 6812130
    Abstract: A method for forming a dual damascene structure for a semiconductor device, in accordance with the present invention, includes providing conductive regions on a first layer, forming an interlevel dielectric layer over the first layer and forming an etch stop layer over the interlevel dielectric layer. The etch stop layer includes a polymer material having a dielectric constant of less than about 3.0. The etch stop layer is patterned to form a via pattern, and a trench dielectric layer is deposited on the etch stop layer and in holes of the via pattern. Trenches are formed in the trench dielectric layer by etching the trench layer in accordance with a trench pattern, and vias are formed in the interlevel dielectric layer by etching through the trenches using the etch stop layer to self-align the trenches to the vias and expose the conductive regions on the first layer.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Gabriela Brase
  • Inductive element of an integrated circuit
    Patent number: 6812819
    Abstract: An inductive element (10) of an integrated circuit, comprising at least one turn (12), which is formed by an integrated elongated track (14) made of a conductive material, wherein the interior margin of the conductive track (14) comprises at least one recess (30). The invention makes it possible in particular to increase the inductivity of the element (10) in a given available space on the substrate of an integrated circuit.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: November 2, 2004
    Assignee: Xignal Technologies AG
    Inventors: Grégoire Le Grand de Mercey, Christophe Holuigue
  • Analog-to-digital converter and method for converting an analog signal into a digital signal
    Patent number: 6812880
    Abstract: The invention relates to an analog-to-digital converter (301), comprising several comparators (303) and a reference network, said reference network having several reference elements (302). At least one input (304) of at least one comparator (303) is connected between the individual reference elements (302) of the reference network in the analog-to-digital converter (301), respectively. A digital evaluation circuit (311) with which the statistical evaluation of the output signals generated by the comparators (303) can be carried out is linked to the outputs (309) of the comparators of the analog-to-digital converter (301). The invention also relates to a corresponding method for converting an analog signal (Ua) into a digital signal (D).
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Christian Paulus
  • Method for roughening a surface of a semiconductor substrate
    Patent number: 6812094
    Abstract: A method for roughening a surface of a semiconductor substrate includes the steps of placing the substrate in a furnace, introducing Oxygen and an inert gas, such as argon or nitrogen, into the furnace, maintaining the oxygen concentration in the furnace below 10%, and annealing the substrate at a temperature between 950° C. and 1200° C. to form mesopores in the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Matthias Goldbach, Annalisa Cappellani
  • Circuit configuration for a current switch of a bit/word line of a MRAM device
    Patent number: 6813181
    Abstract: A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Hans Viehmann, John K. DeBrosse
  • Field effect controlled semiconductor component
    Patent number: 6812524
    Abstract: A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the semiconductor body, and a drift path that is formed between the channel zone and the first connection zone and contains a compensation zone. The compensation zone has a complementary conduction type with respect to the drift zone and includes at least two segments. A distance between the two adjacent segments is chosen such that the punch-through voltage between these segments lies in a voltage range that corresponds to the voltage range assumed by the voltage drop across the drift path at currents situated between the rated current and twice the rated current.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Jens-Peer Stengl, Jenoe Tihanyi, Hans Weber, Gerald Deboy, Helmut Strack, Armin Willmeroth
  • Memory device and method of outputting data from a memory device
    Patent number: 6813193
    Abstract: A method of outputting data from a memory device, such as a dynamic random access memory, is disclosed. The method comprises the steps of providing an integrated circuit having a plurality of memory arrays; separately buffering data from separate memory arrays of the plurality of memory arrays; multiplexing buffered data from the separate memory arrays; and outputting the buffered data from the memory device. A circuit for employing the method is also disclosed.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies, AG
    Inventor: Thomas Vogelsang
  • Memory access method and circuit configuration
    Patent number: 6813695
    Abstract: A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled to the microprocessor. The reversal is randomly controlled. This disguises the current profile of cache hit and miss events, which enhances the security against statistical attack techniques based on the evaluation of the current profile.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Michael Smola
  • Crystal oscillator circuit having capacitors for governing the resonant circuit
    Patent number: 6812801
    Abstract: A crystal oscillator circuit has capacitors that govern the resonant circuit and are designed such that they can be connected and disconnected, for frequency adjustment. A respective compensation capacitor is connected opposite and in mirror-image form to these capacitors that govern the resonant circuit. This compensation capacitor influences only the dynamic operating point, but has virtually no effect on the oscillation frequency. In consequence, it is not possible to shift the operating point during adjustment of the oscillation frequency, thus ensuring stability of the oscillating system and operation at the desired operating point.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Heiko Körner
  • ACS unit for a viterbi decoder
    Patent number: 6813744
    Abstract: An ACS unit is proposed for a Viterbi decoder, which, in order to determine the path metrics of two states of a time step in a trellis diagram, compares the difference (&Ggr;) between the path metrics of the two states (19, 20) which are linked via branches to these two states in the form of a butterfly structure, of the preceding time step in the trellis diagram, with the difference (&Lgr;) between the corresponding branch metrics. The structure of the ACS unit is simplified in that the mathematical signals (sg(&Ggr;), sg(&Lgr;)) of the two differences are also evaluated.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Mario Traeber
  • Recessed metal lines for protective enclosure in integrated circuits
    Patent number: 6812141
    Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: November 2, 2004
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Michael C. Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O'Sullivan, Gregory Costrini, Stephen L. Brown, Frank Findeis, Chanro Park
  • Apparatus for converting a digital value into an analog signal
    Patent number: 6812877
    Abstract: An apparatus converts a digital value including “a” bits into an analog signal and has 2b D/A converters. Here, b is an integer number that is greater than 0. Each of the D/A converters is designed to convert a digital value having “a−b” bits. The digital value that is supplied (for i=1 . . . 2b) to the ith D/A converter for the purpose of D/A conversion corresponds to the “a−b” most significant bits in the sum of the digital value that will be converted by the apparatus and to i−1. The output signal for the apparatus is the mean value for the output signals from the D/A converters. Such an apparatus can be produced such that it can be accommodated easily and efficiently on a semiconductor chip and, irrespective of the details of protocol implementation, permits a completely linear conversion of the digital value being converted into an analog signal.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Marco Bachhuber, Ralf-Rainer Schledz
  • Bipolar transistor and method of producing same
    Publication number: 20040212045
    Abstract: In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.
    Type: Application
    Filed: January 23, 2004
    Publication date: October 28, 2004
    Applicant: Infineon Technologies AG
    Inventors: Armin Tilke, Kristin Schupke
  • Semiconductor component having at least two chips which are integrated in a housing and with which contact is made by a common contact chip
    Publication number: 20040212057
    Abstract: A semiconductor component, featuring a housing, at least two semiconductor chips arranged in the housing, which chips in each case have a front side and a rear side and in each case have at least one contact area at the front and/or rear side, at least one contact clip, which projects from the housing, within the housing, and which has a plate-type section with a first and a second connection area which are opposite one another, and which makes contact with at least two of the chips, its first connection area being applied to the contact area of at least one of the chips and its second connection area being applied to the contact area of at least another of the chips.
    Type: Application
    Filed: January 29, 2004
    Publication date: October 28, 2004
    Applicant: Infineon Technologies AG
    Inventor: Ralf Otremba
  • MOSFET circuit having reduced output voltage oscillations during a switch-off operation
    Publication number: 20040212419
    Abstract: The invention relates to a MOSFET circuit having reduced output voltage oscillations, in which a smaller CoolMOS transistor (T2) with a zener diode (Z1) connected upstream of its gate is located in parallel with a larger CoolMOS transistor (T1), so that, during a switch-off operation, after the larger transistor has been switched off, the smaller transistor (T2) carries a tail current on account of the zener voltage still present, which tail current attenuates output oscillations of the voltage.
    Type: Application
    Filed: January 15, 2004
    Publication date: October 28, 2004
    Applicant: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Device and method for calculating a result of a modular exponentiation
    Publication number: 20040215685
    Abstract: In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and two sub-moduli. In order to improve the safety of the RSA CRT calculations against cryptographic attacks, a randomization of the auxiliary exponents and/or a change of the sub-moduli are performed. Thus, there is a safe RSA decryption and RSA encryption, respectively, by means of the calculating time efficient Chinese Residue Theorem.
    Type: Application
    Filed: February 27, 2004
    Publication date: October 28, 2004
    Applicant: Infineon Technologies AG
    Inventors: Jean-Pierre Seifert, Joachim Velten
  • Optical filter and optical filtering method
    Patent number: 6810174
    Abstract: An optical signal alternately traverses a total of n couplers and n−1 DGD units, arranged therebetween, with a differential group delay between two signal modes. The power division between the two signal modes is measured in each DGD unit in a power division controller, and a signal that is proportional to the difference between the powers in the two signal modes is obtained. The signal is led to an integrating controller whose control signal is led to a differential phase shifter that is accommodated in the DGD unit present upstream in the beam path. The difference between the powers of the two signal modes is thereby brought to zero at least approximately. This has the consequence that it is essentially only the chromatic dispersion that is generated or equalized, but no other disturbing distortions of the optical signal are produced.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: October 26, 2004
    Assignee: Infineon Technologies AG
    Inventors: Zhan Gao, Reinhold Noé
  • Method for producing a semiconductor structure, and use of the method
    Patent number: 6809019
    Abstract: A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are produced, and, after removal of the masking layer and application of an auxiliary layer, the auxiliary layer and the fences are removed jointly except for a predetermined extent of the auxiliary layer. The present invention also relates to use of the method for producing spacers in a semiconductor structure.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 26, 2004
    Assignee: Infineon Technologies AG
    Inventors: Walter Hartner, Matthias Krönke
  • Field effect transistor and method for producing a field effect transistor
    Patent number: 6809379
    Abstract: The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: October 26, 2004
    Assignee: Infineon Technologies AG
    Inventor: Franz Kreupl
  • Geometric beamsplitter and method for its fabrication
    Patent number: 6809871
    Abstract: A method for fabricating a geometric beamsplitter involves applying a reflective coating having at least one metallic layer to a transparent substrate. A pattern of holes containing numerous holes that are preferably randomly distributed over its reflective surface is created in the reflective coating using laser processing. The method allows inexpensively fabricating beamsplitters that have accurately defined transmittances. Beamsplitters in accordance with the invention are suitable for use as dosimetry mirrors on, for example, the illumination systems of microlithographic projection exposure systems.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: October 26, 2004
    Assignee: Carl Zeiss Semiconductor Manufacturing Technologies AG
    Inventors: Matthias Heller, Werner Kress, Matthias Kuhn, Stefan Weissenrieder