Abstract: A protective circuit for limiting a voltage at a pad of an integrated circuit includes a threshold selector connected between the pad and ground. The input voltage to the threshold selector is the pad voltage. The threshold detector includes a first transistor where load path is connected to the pad. The central terminal of the first transistor is maintained at a threshold voltage derived from the pad voltage. A second transistor has its control terminal connected to a second terminal of the load path of the first transistor. The load path of this second transistor is connected between the pad and ground.

Abstract: A machining apparatus (10) comprises a material removing tool (12) movably mounted for removing material from a workpiece (14); means for illuminating (42, 54) a sample area upon a tool surface (34) with excitation radiation; means for receiving (42, 54) sample light emitted from the sample area; a spectral analyzer (54) for performing a spectral analysis of the sample light received; and means for determining (60) the condition of the tool at the sample area from the spectral analysis of the sample light. The wear of the tool (12) is determined as such a condition. Operation parameters of the machining apparatus (10) are adjusted according to the determined wear. An example application is a wafer dicing tool.

Abstract: In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier and a diffusion barrier is used to reliably prevent diffusion of impurities between element layers. This allows semiconductor circuits to be produced with smaller structure sizes and with a higher integration density.

Abstract: A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage. The apparatus includes a differential load having two MOS transistors of unequal channel width/length ratios. The differential load implements a square and summing function in a single circuit eliminating the need to split the signal path.

Abstract: The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from a die to a predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies.

Abstract: An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the access control circuits results in a blocking of the data output circuits.

Abstract: The method for mains-synchronous switching of circuit breakers comprises the following method steps:

Abstract: A storage cell configuration including magnetoresistive storage elements located in a cell field between first lines and second lines. A first metalization plane, a second metalization plane and contacts connecting the first metalization plane to the second metalization plane are provided in a periphery. The first lines and the first metalization plane and the second lines and the contacts are disposed on the same plane respectively so that they can be produced by structuring one conductive layer respectively.

Abstract: A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a deviation between the original layout and a subsequent layout of a mask derived from said original layout. On the basis of this deviation, new data defining a new layout is calculated. This new layout is more similar to the subsequent layout that it is to the original layout.

Abstract: A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one semiconductor chip, external contacts and a conductor configuration. The intermediate layer is provided with at least one opening, into which the at least one semiconductor chip is inserted. The carrier layer, the intermediate layer and the coverlayer are connected one above another and form a submodule. If a plurality of submodules are installed above one another, a semiconductor component is provided in which the semiconductor chips are located in several mutually overlying planes. The semiconductor chips can be interconnected. A method for producing a semiconductor component is also provided.

Abstract: Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip.

Abstract: The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.

Abstract: Fourier transformations are used to calculate a power spectrum of an image of an integrated circuit. The distance between periodic structures is determined from the first refraction maximum, which represents the reciprocal of the distance between the periodic structures. This enables performance of a simple method for calculating the distances between the periodic structures on integrated circuits or photomasks.

Abstract: A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate is provided below the selection transistors in a semiconductor body. A method of fabricating a semiconductor memory configuration is also provided.

Abstract: A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the first layer with a partial or complete local layer erosion to form raised and recessed layer regions, and depositing a second layer. The structured first layer is a provided as a permanently remaining layer. Edges are formed at transitions from raised to recessed layer regions. The height difference at the edges of the structured first layer separates individual layer regions of the second layer. The edges of the raised regions act as partition edges for the second layer. A process for producing components of an integrated circuit and a process for producing a memory configuration are also provided.

Abstract: This invention provides a read/write channel with a multiplex input/output system for a disk drive, which may have one or more magnetic disks, one or more read/write heads, and a read/write channel. The read/write channel may comprise a multiplex input/output (I/O) terminal, a write output driver, and a digital to analog converter. The read/write channel may be implemented on an integrated circuit. The multiplex input/output system may send different signals or voltages through the same input/output terminal at essentially at the same time or different periods of time.

Abstract: An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The antifuse structure is located within an insulated well composed of semiconductor material.

Abstract: An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.

Abstract: A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.