Patents Assigned to Technologies & Devices International, Inc.
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Patent number: 6573164Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).Type: GrantFiled: March 28, 2002Date of Patent: June 3, 2003Assignee: Technologies and Devices International, Inc.Inventors: Denis V. Tsvetkov, Andrey E. Nikolaev, Vladimir A. Dmitriev
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Patent number: 6562124Abstract: A novel method for growing semiconductor material including GaN is disclosed. The method involves placing a first substance into a growth reactor, supplying a second gaseous substance into the grouth reactor, and applying electrical field to the second gaseous substance to produce the cry stalline compound material.Type: GrantFiled: June 2, 2000Date of Patent: May 13, 2003Assignee: Technologies and Devices International, Inc.Inventors: Vladimir Ivantzov, Vitaliy Sukhoveev, Vladimir Dmitriev
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Patent number: 6559467Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.Type: GrantFiled: May 17, 2001Date of Patent: May 6, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6559038Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 18, 2001Date of Patent: May 6, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6555452Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.Type: GrantFiled: May 17, 2001Date of Patent: April 29, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Publication number: 20020174833Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).Type: ApplicationFiled: March 28, 2002Publication date: November 28, 2002Applicant: Technologies & Devices International, Inc.Inventors: Denis V. Tsvetkov, Andrey E. Nikolaev, Vladimir A. Dmitriev
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Publication number: 20020177312Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).Type: ApplicationFiled: March 28, 2002Publication date: November 28, 2002Applicant: Technologies & Devices International, Inc.Inventors: Denis V. Tsvetkov, Andrey E. Nikolaev, Vladimir A. Dmitriev
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Patent number: 6479839Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 18, 2001Date of Patent: November 12, 2002Assignee: Technologies & Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6476420Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 17, 2001Date of Patent: November 5, 2002Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6472300Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 18, 2001Date of Patent: October 29, 2002Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Publication number: 20020155713Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).Type: ApplicationFiled: March 28, 2002Publication date: October 24, 2002Applicant: Technologies & Devices International, Inc.Inventors: Denis V. Tsvetkov, Andrey E. Nikolaev, Vladimir A. Dmitriev
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Patent number: 6218269Abstract: A process is disclosed for producing pn junctions and p-i-n junctions from group III nitride compound semiconductor materials. The process comprises growing of pn junctions and p-i-n junctions by hydride vapor phase epitaxy employing hydride of nitrogen (ammonia, hydrozine) as a source of nitrogen and halides of group III metal as a source of metal. Mg is used as acceptor impurity to form p-type III-V nitride layers. The preferred sources for Ga and Al are Ga and Al metals, respectively. The process is carried out in the temperature range from 900 to 1200° C.Type: GrantFiled: November 18, 1998Date of Patent: April 17, 2001Assignee: Technology and Devices International, Inc.Inventors: Andrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev