Patents Assigned to Technology Corporation
  • Patent number: 6946914
    Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: September 20, 2005
    Assignee: Linear Technology Corporation
    Inventor: Steven D. Roach
  • Patent number: 6946455
    Abstract: Compounds represented by the general formula (I): which two DNA strands can be interstrand-crossliked: A-L-B-X-B-L-A??(I) wherein B represents a chemical structure capable of recognizing the nucleotide sequence of DNA; A represents a chemical structure capable of binding to one of the bases of DNA; L represents a linker by which the chemical structures of A and B can be linked to each other; X represents a spacer by which the A-L-B components can be linked to each other. A method of interstrand-crosslinking DNA by using these compounds; and medicinal compositions containing interstarand-crosslinking agents of DNA.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: September 20, 2005
    Assignee: Japan Science and Technology Corporation
    Inventors: Hiroshi Sugiyama, Toshikazu Bando, Hirokazu Iida, Isao Saito
  • Patent number: 6946670
    Abstract: An inspection system to inspect structures on a substrate. A generator directs a primary beam at the substrate along a selectable angle, thereby producing a secondary beam having properties that are characteristic of the structures on the substrate. At least one of the substrate and the primary beam are scanned relative to the other at a selectable speed. A sensor receives the secondary beam and provides analog signals having properties that are characteristic of the secondary beam. An analog to digital converter receives the analog signals and provides digital signals having properties that are characteristic of the analog signals. A controller receives the digital signals and determines the properties of the structures on the substrate based at least in part on the properties of the digital signals.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 20, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: Larry Zurbrick
  • Patent number: 6944935
    Abstract: A method of forming a rotor for a positive displacement motor. The method includes forming a liner that includes at least two resilient layers and at least one fiber layer, and the at least two resilient layers are positioned so as to enclose the at least one fiber layer. The liner is positioned on a rotor tube, and the rotor tube includes a shaped outer surface including at least two radially outwardly projecting lobes extending helically along a selected length of the rotor tube. The liner is cured on the rotor tube so that the liner conforms to the radially outwardly projecting lobes formed on the outer surface and to the helical shape of the outer surface. The curing forms a bond between the liner and the outer surface and between the at least two resilient layers and the at least one fiber layer.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: September 20, 2005
    Assignee: Schlumberger Technology Corporation
    Inventor: Jean-Michel Hache
  • Patent number: 6945506
    Abstract: A through-insulation connector assembly for use in the construction of insulated concrete sandwich wall. The connector assembly includes a spool-shaped connector body comprised of two, interconnecting pieces and a tie that engages the connector body. The two pieces of the connector body are installed at the place of manufacture in a sheet of foam insulation board that will be used as the insulation layer in the construction of an insulated concrete sandwich wall.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: September 20, 2005
    Assignee: Composite Technologies Corporation
    Inventor: Robert T. Long, Sr.
  • Patent number: 6947241
    Abstract: An asynchronous method for locating individual blocks of data in a tape drive, without having to read the blocks of data is provided. The invention comprises placing an ID mark adjacent to the data blocks and inter-block gaps on the tape. The ID mark contains a small amount of information about the next respective data block on the tape. The ID mark is encoded such that the same detection mechanism that detects the inter-block gap can also retrieve the ID mark information, without having to process the entire block of data associated with a particular ID mark. The ID mark is symmetrical such that it can be detected and decoded in the forward and backward direction, allowing the tape drive to find a desired block of data by searching either forward or backward, even when the magnetic tape uses a unidirectional data format.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 20, 2005
    Assignee: Storage Technology Corporation
    Inventors: Richard Allen Gill, Roger D. Hayes, Keith Gary Boyer
  • Patent number: 6945831
    Abstract: An electrical connector includes a hollow conductive post member having a circular periphery, a foot portion and a distal end. The distal end has a generally cup shaped indentation. A base member is included having top and bottom surfaces. The foot portion of the post member is mounted to the top surface. At least one standoff extends from the bottom surface of the base member. The at least one standoff is for resting against a contact surface when soldering the electrical connector to the contact surface, thereby separating the bottom surface from the contact surface to define a minimum volume therebetween for occupation by solder.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: September 20, 2005
    Assignee: Antaya Technologies Corporation
    Inventors: John Pereira, Manuel Machado, Stephen Antaya
  • Patent number: 6946598
    Abstract: An EMI shielding gasket for reducing the amount of force required during the mounting process. The present invention provides an extended lip feature on the gasket to facilitate the installation process and to function as a lead-in, such that less force is required by the assembler when mounting the EMI gasket. As less manipulation may be required to install the gaskets, gaskets may be mounted correctly more often, thereby preventing the occurrence of EMI leakage. The present invention also reduces the possibility that the EMI gaskets may become damaged due to excess manipulation, and assemblers may experience fewer physical problems related to manipulating the gaskets. By reducing the amount of force required to mount the EMI gaskets, the present invention may increase productivity by decreasing assembly time, decrease rework of improperly assembled or damaged gaskets, and reduce health risks and subsequent insurance claims of assemblers during manufacturing.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: September 20, 2005
    Assignee: Storage Technology Corporation
    Inventor: Michael Vaughn Konshak
  • Patent number: 6947514
    Abstract: A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Kazuo Kato, Takashi Sase, Takashi Hotta, Hirokazu Aoki, Kozaburo Kurita
  • Patent number: 6946344
    Abstract: A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: September 20, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Shih-Chung Chou, Yi-Nan Chen, Tzu-Ching Tsai
  • Patent number: 6948141
    Abstract: Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: September 20, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Akella V. S. Satya, Vladimir D. Federov, Li Song
  • Patent number: 6946665
    Abstract: A charged particle beam exposure apparatus which exposes a substrate using a plurality of charged particle beams includes a first measurement member for making the plurality of charged particle beams come incident and measuring a total current value of the charged particle beams. A second measurement member makes the plurality of charged particle beams come incident and multiplies electrons of each of the incident charged particle beams, thereby measuring a relative value of a current of each of the charged particle beams.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: September 20, 2005
    Assignees: Canon Kabushiki Kaisha, Hitachi High-Technologies Corporation
    Inventors: Masato Muraki, Yoshinori Nakayama, Hiroya Ohta, Haruo Yoda, Norio Saitou
  • Patent number: 6946678
    Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: September 20, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo Ching Jiang
  • Patent number: 6946674
    Abstract: A low-dimensional plasmon-light emitter for converting an inputted electric energy luminescence with an arbitrary energy over a broad range. The emitter has a low-dimensional conductive structure incorporated inside or in a surface layer of a semiconductor or dielectric. A periodic nanostructure is incorporated in the vicinity of or inside the low-dimensional conductive structure. The low-dimensional conductive structure may be a quantum well formed inside a semiconductor or dielectric, a space-charge layer formed on a surface or heterojunction of a semiconductor or dielectric, or a surface or interface electronic band with high carrier density formed on a surface or heterojunction of a semiconductor or dielectric.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: September 20, 2005
    Assignee: Japan Science and Technology Corporation
    Inventor: Tadaaki Nagao
  • Patent number: 6945331
    Abstract: The multiple interventionless actuated downhole valve includes a valve movable between an open and a closed position to control communication between an annular region surrounding the valve and an internal bore and more specifically controlling communication between above and below the valve, and at least two remotely operated interventionless actuators in operational connection with the valve, wherein each of the interventionless actuators may be operated independently by absolute tubing pressure, absolute annulus pressure, differential pressure from the tubing to the annulus, differential pressure between the annulus and the tubing, tubing or annulus multiple pressure cycles, pressure pulses, acoustic telemetry, electromagnetic telemetry or other types of wireless telemetry to change the position of the valve and allowing the valve to be continually operated by mechanical apparatus.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: September 20, 2005
    Assignee: Schlumberger Technology Corporation
    Inventor: Dinesh R. Patel
  • Patent number: 6946865
    Abstract: A semiconductor integrated circuit apparatus includes a first controlled circuit halving at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Hiroyuki Mizuno, Koichiro Ishibashi, Susumu Narita
  • Patent number: 6947491
    Abstract: A method and apparatus are disclosed for deinterleaving expanded interleaved data blocks, particularly for use in a wireless telecommunications system such as provided by the Third Generation Partnership Project (3G) standard. The data is processed on a sequential element basis where each element has a pre-determined number of bits M which bits are contained in a block of sequential data words W?. The elements are extracted from the block of words W? in sequential order, each element being extracted from either a single or two sequential interleaved words within the set of words W?. The elements are stored in selective location within a set of words W of a deinterleaver memory such that upon completion of the extraction and writing of all the elements, the words W from the deinterleaver memory can be sequentially read out to correspond to an original data block of bits from which the block of interleaved elements was created.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: September 20, 2005
    Assignee: InterDigital Technology Corporation
    Inventor: Sharif M. Shahrier
  • Patent number: 6946016
    Abstract: Contemplated configurations and methods include a hydrogen pressure swing adsorption unit that receives a feed gas comprising a hydrogen production stream and a non-recycled hydrogen-containing waste stream.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 20, 2005
    Assignee: Fluor Technologies Corporation
    Inventor: Satish Reddy
  • Patent number: 6947852
    Abstract: A system and method for assessing and potentially correcting for non-translational motion in a resonance measurement apparatus is provided. The design measures the response of an article, such as an HGA assembly including a read/write head, as well as the excitation of a shaking device, such as a head resonance tester, and computes a correction factor using either two or three point measurement. The correction factor may be evaluated by subjecting the arrangement to further vibration at varying frequencies. Measurement of the shaking device may be accomplished using an accelerometer or by optical measurement using a light beam.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 20, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Harald F. Hess, Patrick Rodney Lee
  • Patent number: D509917
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: September 20, 2005
    Assignee: Toshiba Lighting & Technology Corporation
    Inventor: Kazuo Egawa
  • Patent number: 5004561
    Abstract: An electromagnetic wave-shielding thermoplastic resin composition comprising(A) 100 parts by weight of a thermoplastic resin selected from the group consisting of polypropylene resins, polystyrene resins, acrylonitrile/styrene/butadiene copolymer resin, polybutylene terephthalate resins, polyphenylene ether resins and linear aliphatic polyamide resins,(B) 30 to 300 parts by weight of electrically conductive glass fibers,(C) 5 to 40 parts by weight of carbon black, and(D) 5 to 40 parts by weight of graphite.
    Type: Grant
    Filed: January 23, 1989
    Date of Patent: April 2, 1991
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Isao Nomura, Kenichi Narita