Abstract: A signal isolation device includes an insulation layer, at least one metal foil unit, and a metal layer. The at least one metal foil unit is disposed on a top surface of the insulation layer, and the metal foil unit has a first recessed channel and a second recessed channel. The first recessed channel and the second recessed channel spirally extend inward from an edge of the metal foil unit, and the first recessed channel and the second recessed channel surrounding each other are spaced apart. The metal layer is disposed on a bottom surface of the insulation layer.

Abstract: A discriminator of a training model is trained to discriminate between original training images without artificial subsurface data and modified training images with artificial subsurface data. A generator of the training model is trained to: replace portions of original training images with the artificial subsurface data to form the modified training images, and prevent the discriminator from discriminating between the original training images and the modified training images.

Abstract: A method includes training a proxy model to predict output from a reservoir model of a subterranean volume, receiving data representing an oilfield operation performed at least partially in the subterranean volume, predicting one or more performance indicators for the oilfield operation using the proxy model, and updating the reservoir model based at least in part on the one or more performance indicators predicted in the proxy model.

Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.

Abstract: Process for interpreting one or more borehole images for use in drilling operations. In some embodiments, the process can include providing an input borehole image obtained from a downhole measurement provided by one or more downhole sensors. The process can also include collecting contextual information relative to the borehole image and the user. The process can also include using the collected contextual information and a mathematical model to infer one or more processing arguments. The mathematical model can be defined by using previously collected arguments and previously collected contextual information. The process can also include processing the input borehole image with the one or more inferred processing arguments to generate one or more interpreted borehole images. The process can also include adjusting one or more drilling operation based, at least in part, on the one or more interpreted borehole images.

Abstract: The present invention is directed to non-naturally occurring peptides containing a membrane-penetrating amino acid sequence and further at least one polycationic moiety or peptide sequence. The peptides are suitable for use in delivery a cargo to the interior of a cell. Suitable cargo includes nucleic acid molecules (including DNA, RNA or PNA), polypeptides, or other biologically active molecules. The present invention is further directed to transfection complexes containing the non-naturally occurring peptides of the present invention in non-covalent association with at least one cationic lipid and a cargo to be delivered to the interior of a cell. The invention further relates to methods for the preparation and use of the non-naturally occurring peptides for the formation of transfection complexes and the delivery of a cargo to the interior of a cell in culture, an animal or a human. The invention also relates to compositions and kits useful for transfecting cells.

Abstract: A testing method includes the following steps of: accessing a memory chip to put the memory chip into a write leveling mode; inputting a strobe signal into the memory chip under the write leveling mode; adjusting signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip under the write leveling mode; generating a data signal according to the strobe signal under the write leveling mode; and determining types of the memory chip according to the data signal under the write leveling mode.

Abstract: A method includes: obtaining an image of a keyboard layout; detecting, from the image, a plurality of key boundaries; determining a label string for a portion of the image defined by a corresponding key boundary from the plurality of key boundaries; selecting, for the determined label string, a corresponding key action; generating a keyboard layout definition for the image of the keyboard layout, the keyboard layout definition including a key definition for the corresponding key boundary, the key definition having: (i) a position for rendering of a key, (ii) a label configured to be rendered at the position of the key, and (iii) an action configured to be caused by selection of the key; and communicating the keyboard layout definition for deployment to a mobile device.

Abstract: An electronic device includes at least two logic circuits, at least two memories, and at least two power switches. The logic circuits are stacked on each other and electrically connected to each other, and they are electrically connected between a power source and a ground. The memories are stacked on each other and electrically coupled to each other, and they are electrically connected between the power source and the ground. The power switches are connected in series between the respective logic circuits and the respective memories. The power switches cut off or maintain the electrical connection between the logic circuits and between the memories, according to a control signal.

Abstract: A brake control system includes one or more processors communicatively connected to at least one sensor configured to output at least one property measurement of air in a brake pipe of a vehicle braking assembly. The one or more processors are configured to determine, based on the at least one property measurement, a pressure reduction lower limit (PRLL) in the brake pipe. The one or more processors are further configured to control movement of a vehicle system that includes the brake pipe to enforce the PRLL by preventing a pressure reduction in the brake pipe that is less than the PRLL while one or more air reservoirs of the vehicle braking assembly are at a reduced charge state.

Abstract: An optical member includes a light guide body. The light guide body has an incident surface on which an outside light is incident, a first surface having flat portions and prism portions, an incident light incident on the incident surface reaching the first surface for the first time, and a second surface arranged opposite to the flat portions. The flat portions totally reflect the incident light toward the second surface. The second surface totally reflects a reflected light reflected by the flat portion toward the first surface. The prism portion has an ejection surface to emit the incident light to outside.

Abstract: A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.

Abstract: A method for evaluating drill cuttings includes acquiring a first digital image and processing the first digital image with a trained neural network (NN) to generate a first segmented image including a plurality of labeled segments in which at least one label includes a lithology type. The segmented image and the acquired first digital image are processed to retrain the NN. A second digital image is then be processed with the retrained NN to generate a second segmented image including a plurality of labeled segments in which at least one label includes a lithology type.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes an isolation layer positioned in a substrate to define a first surrounding area surrounding a center area; a first guard ring in the first surrounding area; and a programmable unit including: a middle insulating layer in the center area and including a U-shaped cross-sectional profile; a first electrode including a common layer on two sides of the middle insulating layer, and a connection layer including a U-shaped cross-sectional profile, on the two sides and the bottom surface of the middle insulating layer, and connecting to the common layer; and a second electrode layer on an inner surface of the middle insulating layer. A bottom surface of the common layer is at a vertical level greater than a vertical level of a bottom surface of the middle insulating layer.

Abstract: A packer for a blowout preventer includes an elastomer body and one or more inserts coupled to the elastomer body. At least one insert of the one or more inserts includes an insert body with an elastomer-contacting surface and one or more fixed extensions that extend from the elastomer-contacting surface to engage the elastomer body.

Abstract: An aluminum alloy film includes an Al—Si—Mg alloy film containing at least 0.9% by weight to 1.1% by weight of Si and 0.1% by weight to 2.3% by weight of Mg, and the Al—Si—Mg alloy film contains Mg silicide crystals in Al crystals. A semiconductor device includes multiple gate trench structures, an interlayer insulating film covering the trench gate structures, an electrode film covering the interlayer insulating film, an insulating layer and a conductive layer covering the electrode film. The electrode film includes the Al—Si—Mg alloy film.

Abstract: Disclosed is a multiple segment well tool (10), the multiple segment well tool comprising a first tool segment having a first shaft (32) rotatably supported in a first tool segment housing (30-1); a connector housing (30A) releaseably connected at one end to one end of the first tool segment housing, and a second tool segment housing (30-2) releaseably connected at one end to another end of the connector housing. The connector housing comprises a piston (34) disposed therein, the piston movable along a longitudinal dimension of the connector housing.

Abstract: A method includes receiving seismic data related to a subterranean formation. The method also includes receiving a selection of a property of the subterranean formation that is permitted to vary during a simulation of a model of the subterranean formation. The method also includes simulating fluid flow in the model of the subterranean formation based at least partially on the seismic data, and the selected property. The method also includes generating an updated model based at least partially upon a result of simulating the fluid flow in the model.

Abstract: A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.