Abstract: A processor which expands a compressed video signal is disclosed. The compressed video signal applied to the processor is generated by partitioning a video image into segments and then describing how each segment is filled by using a bilinear equation, that is to say, a linear equation which is a function of a horizontal coordinate X and a vertical coordinate Y. The coefficients of the X and Y coordinates each include integer and fractional parts. The circuitry develops a table of values from the coefficient of the X coordinate by repeatedly adding the coefficient in an accumulator. As each sum is produced, the integer part of the sum is stored. The table of values is developed from the stored integer sums as the difference between alternate sums, where successive alternate pairs of sums are interleaved. For example, the table would include the difference between the first and third sums followed by the difference between the second and fourth sums, then the third and fifth sums and so on.

Abstract: A display processor, as for a small computer, processes pixel codes of various lengths. Three addressable color maps have their read addresses generated independently from portions of each pixel code. The portions of each pixel code used in generating each read address can be selected by programming.