Abstract: A signal processing apparatus receives an input acoustic signal, acquires a first acoustic signal having a periodic variation corresponding to the frequency of gamma waves, and outputs an output acoustic signal based on the acquired first acoustic signal and the second acoustic signal. The second acoustic signal is based on the input acoustic signal.

Abstract: Provided is an integrated antenna package structure including a chip, a circuit structure, a shielding body, an encapsulant, a first antenna layer, a dielectric body, and a second antenna layer. The circuit structure is electrically connected to the chip. The shielding body is disposed on the circuit structure and has an accommodating space. The chip is disposed in the accommodating space of the shielding body. The encapsulant is disposed on the circuit structure and covers the chip. The first antenna layer is disposed on the circuit structure and is electrically connected to the circuit structure. The dielectric body is disposed on the encapsulant. The second antenna layer is disposed on the dielectric body. A manufacturing method of the integrated antenna package structure is also provided.

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

Abstract: A package structure includes at least two semiconductor structures that are stacked onto one another. The first surface of one semiconductor structure of the at least two semiconductor structures that are stacked onto one another directly faces toward the second surface of another semiconductor structure of the at least two semiconductor structures which is adjacent to said one semiconductor structure; the first metal layer of said one semiconductor structure is in contact with and bonded to the third metal layer of said another semiconductor structure; and the second metal layer of said one semiconductor structure is in contact with and bonded to the fourth metal layer of said another semiconductor structure.

Abstract: A computer-implemented method for facilitating cardiac rehabilitation among eligible users is disclosed. The method includes the steps of (1) receiving health information associated with one or more users; (2) for each user of the one or more users: determining, based on health information associated with the user, a respective eligibility of the user for cardiac rehabilitation; (3) determining, based on the respective eligibilities, that at least one user of the one or more users is eligible for cardiac rehabilitation; (4) generating a treatment plan for the at least one user, where the treatment plan pertains to a cardiac rehabilitation that is specific to the at least one user; and (5) assigning the treatment plan to at least one electromechanical machine to enable the user to perform the cardiac rehabilitation.

Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.

Abstract: Group identity assignment and policy enforcement may be provided. A User Defined Network Identifier (UDN ID) defining a group of client devices may be received. Next, a client identifier (ID) associated with a source client device that is associated with the group of client devices may be received. The UDN ID and the client ID may be encoded in an Extended Local Identifier (ELI) Media Access Control (MAC) address associated with the source client device. A source MAC address of a packet received from the source client device may then be substituted with the ELI MAC address. Then the packet may be forwarded.

Abstract: The present application relates to the field of semiconductor manufacturing technologies, and in particular to a method and an apparatus for automatically processing wafers. The method for automatically processing the wafers includes the following steps: providing several wafers, wherein the wafers operate on a primary path, and the primary path is a path for forming semiconductor structures on the surfaces of the wafers; determining whether there is a need for detecting defects of the wafers, and if yes, automatically switching an operating path of the wafers to a secondary path; detecting the defects of the wafers in the secondary path; and determining whether the defect detection on the wafers is finished, and if yes, automatically switching the operating path of the wafers to the primary path. The application makes it possible to automatically detect the defects of the wafers with different SWR conditions, thereby improving the automation degree of machines.

Abstract: A pulse oximetry system including a housing operable to interface with a digit of a user, a light emitter, and first and second light receivers. The light emitter is positioned adjacent to an inside surface of the housing and operable to emit a light, the light configured to transmit through tissue of the digit of the user, wherein some of the light is scattered by or reflected off the tissue of the digit of the user. The first light receiver is positioned adjacent to an inside surface of the housing opposite from the previously mentioned inside surface and operable to detect light that is transmitted through the tissue of the digit of the user. The second light receiver adjacent to an inside surface of the housing and operable to detect light that is scattered by or reflected off the tissue of the digit of the user.

Abstract: A unidirectional-driven drug infusion device, includes: a reservoir, a piston and a screw, the piston is arranged in the reservoir; a driving module which includes at least one driving wheel and at least one driving arm that cooperate with each other, the circumferential surface of the driving wheel is provided with wheel teeth; a power module coupled to the driving arm; a control module, connected to the power module, controls the power module to apply different driving powers to the driving arm, making the driving arm perform linear reciprocating motion; and a friction member which is in contact with the surface of the driving wheel. This device can fully utilize the internal space of the infusion device, and its weight and volume is reduced.

Abstract: Apparatuses and methods of overlay measurement are disclosed. An example apparatus includes: a substrate comprising first material; a first layer comprising second material disposed on a surface of in the substrate; a first alignment pattern including third material disposed in the first layer; and a second layer above the first layer including a second alignment pattern. A difference between refractive indexes of the second material and the third material is greater than a difference between refractive indexes of the first material and the third material.

Abstract: A field-effect transistor includes an n-type semiconductor layer that includes a Ga2O3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.

Abstract: Computer systems and associated methods are disclosed to implement a model development environment (MDE) that allows a team of users to perform iterative model experiments to develop machine learning (ML) media models. In embodiments, the MDE implements a media data management interface that allows users to annotate and manage training data for models. In embodiments, the MDE implements a model experimentation interface that allows users to configure and run model experiments, which include a training run and a test run of a model. In embodiments, the MDE implements a model diagnosis interface that displays the model's performance metrics and allows users to visually inspect media samples that were used during the model experiment to determine corrective actions to improve model performance for later iterations of experiments. In embodiments, the MDE allows different types of users to collaborate on a series of model experiments to build an optimal media model.

Abstract: The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.

Abstract: Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to modulate the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request responsive to possession of a credit corresponding to the communication request. In these situations, if the transmitter has exhausted a supply of credits, the transmitter waits until a credit is returned before transmitting another request. The receiver of the requests can manage credit returns based on whether a request queue has space to receive another request. Further, the receiver can delay a credit return based on how many requests are pending at the receiver, even if space is available in the request queue. This delay can prevent an oversupply of requests from developing downstream of the request queue. Latency, for instance, can be improved by managing the presence of requests that are downstream.

Abstract: Improved technology for managing the caching of objects that are rarely requested by clients. A cache system can be configured to assess a class of objects (such as objects associated with a particular domain) for cacheability, based on traffic observations. If the maximum possible cache offloading for the class of objects falls below a threshold level, which indicates a high proportion of non-cacheable or “single-hitter” content, then cache admission logic is configured to admit objects only after multiple clients requests during a time period (usually the object's time in cache, or eviction age). Otherwise, the cache admission logic may operate to admit objects to the cache after the first client request, assuming the object meets cacheability criteria. The technological improvements disclosed herein can be used to improve cache utilization, for example by preventing single-hitter objects from pushing out multi-hit objects (the objects that get hits after being added to cache).

Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.

Abstract: A method for secure wireless communication executed by at least one processor of a device. A registration certificate is transmitted to the device by a host, the registration certificate including a Long Term Device Key (LTDK) and being generated by a registration server in response to the registration of the host as authorized to connect to the device. In response to receiving a request for securing a Bluetooth connection between the device and the host, the device transmits the LTDK to the host. The device receives, from the host, a connection certificate including connection data for establishing the connection between the host and the device. The connection certificate is signed by a private Long Term Host Key (LTHK) of the host, where the LTHK of the host and the LTDK of the device form a cryptographic Long Term Key pair. The device validates the connection certificate using the LTDK of the device to determine whether the host is authorized to connect to the device.

Abstract: A system includes a motor configured to be coupled to a non-rigid load and a control system disposed within, or communicatively coupled to, a drive system configured to control an operation of the motor. The control system includes a processor and a memory accessible by the processor. The memory stores instructions that, when executed by the processor, cause the processor to generate a smooth move input profile to control the operation of the motor based on inputs specifying a desired operation of the motor, apply a notch filter having a notch filter frequency to the smooth move input profile to produce a filtered smooth move input profile, and send a command to the drive system based on the filtered smooth move input profile, wherein the command is configured to adjust the operation of the motor.