Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

Abstract: Systems and methods are described herein for logging system events within an electronic machine using an event log structured as a collection of tree-like cause and effect graphs. An event to be logged may be received. A new event node may be created within the event log for the received event. One or more existing event nodes within the event log may be identified as having possibly caused the received event. One or more causal links may be created within the event log between the new event node and the one or more identified existing event nodes. The new event node may be stored as an unattached root node in response to not identifying an existing event node that may have caused the received event.

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

Abstract: Systems and methods are provided that sense a state of a fuse located in a fuse array. These methods involve a logic gate that selectively transmits outputs from respective comparators based on the combination of outputs received at the logic gate. The comparators generate outputs based on comparing a signal received indicative of the fuse state and a reference voltage. The described systems and methods reduce power consumption of a fuse sensing device since portions of the fuse sensing device are deactivated when not sensing and enable single fuse reading to occur, among other advantages.

Abstract: A system includes an agitation system having a container configured to store a coating material, an agitator configured to agitate the coating material, and a sensor configured to sense conditions within the container and transmit the conditions. The system also includes an agitation control system having a controller configured to turn on the agitator, and change an intensity of agitation in response to an input received from the agitation system.

Abstract: An actuation device may include a plurality of actuation units disposed about an axis. Each actuation unit of the plurality of actuation units may include a shape memory alloy component, an auxetic material component operationally coupled to the shape memory alloy component, and a power source operationally coupled to the shape memory alloy component. Additionally, the actuation device may include a control system operationally coupled to the power source, the control system is configured to actuate the shape memory alloy component through the power source. Further, when actuated, the shape memory alloy component moves in a direction outward from the axis to pull the auxetic material component, and the auxetic material component expands in a direction perpendicular to the movement direction of the shape memory alloy component.

Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

Abstract: Systems, methods, and non-transitory computer readable media are provided for determining routes within a location. Location information for a location may be obtained. The location information may include terrain information for the location. A set of restricted regions within the location may be determined based on the location information. A set of paths within the location may be determined based on the set of restricted regions. An interface through which information describing the set of paths within the location is accessible may be provided.

Abstract: Methods, systems, and devices that support a dynamic screen refresh rate are described. An electronic device may dynamically (e.g., autonomously, while operating) adjust the rate at which a screen is refreshed, such as to balance considerations such as user experience and power consumption by the electronic device. For example, the electronic device may use an increased refresh rate when executing applications for which user experience is enhanced by a higher refresh rate and may use a decreased refresh rate when executing other applications. As another example, the electronic device may use different refresh rates while executing different portions of the same application, as some aspects of an application (e.g., more intense portions of a video game) may benefit more than others from a higher refresh rate. The electronic device may also account of rother factors, such as battery level, when setting or adjusting the refresh rate of the screen.

Abstract: Techniques for facilitating an autonomous operation, such as an autonomous navigation, of an unmanned vehicle based on one or more fiducials. For example, image data of a fiducial may be generated with an optical sensor of the unmanned vehicle. The image data may be analyzed to determine a location of the fiducial. A location of the unmanned vehicle may be estimated from the location of the fiducial and the image. The autonomous navigation of the unmanned vehicle may be directed based on the estimated location.

Abstract: In one embodiment, a method includes detecting a request to route traffic to a service associated with an application. The method also includes identifying an application identifier associated with the application and selecting, using the application identifier, a label from a plurality of labels included in a routing table. The label includes one or more routes. The method further includes routing the traffic to the service associated with the application using the label.

Abstract: A method and devices are disclosed for producing a RTT vector (RTV) that is based upon the change in an airborne measuring station position and the corresponding RTT results taken at known time intervals to a ground based target station. In one embodiment, the target station is an access point or station conforming to the IEEE 802.11 standard and the airborne measuring station 110 may also be a device that conforms to the IEEE 802.11 standard. The disclosed method enables the location of a target station to an accuracy in the order of, for example, less than one half degree of bearing within, for example, a period in the order of 5 seconds.

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between.

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Abstract: Configuring managed devices when a Network Management System (NMS) is not reachable may be provided. First, a first network device in a network may determine that the first network device has a configuration issue. Determining the configuration issue may comprise determining that the first network device needs to be configured and determining that the first network device cannot connect to the NMS. Next, the first network device may determine, in response to determining that the first network device has the configuration issue, that a second network device in the network was configured by the NMS. Then, in response to determining that the second network device was configured by the NMS, the first network device may obtain second network device configuration data from the second network device. The first network device may then be configured with data comprising at least a portion of the second network device configuration data.

Abstract: An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.

Abstract: The present disclosure generally relates to sensor device, such as a magnetic sensor bridge, that utilizes a dual free layer (DFL) structure. The device includes a plurality of resistors that each includes the same DFL structure. Adjacent the DFL structure is a magnetic structure that can include a permanent magnet, an antiferromagnetic (AFM) layer having a synthetic AFM (SAF) structure thereon, a permanent magnetic having a SAF structure thereon, or an AFM layer having a ferromagnetic layer thereon. The DFL structures are aligned with different layers of the magnetic structures to differentiate the resistors. The different alignment and/or different magnetic structures result in a decrease in production time due to reduced complexity and, thus, reduces costs.

Abstract: Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.