Abstract: An immersion-type liquid cooling heat dissipation sink is provided. The immersion-type liquid cooling heat dissipation sink includes a heat dissipation substrate layer and a surface film layer. The surface film layer is formed on the heat dissipation substrate layer. The heat dissipation substrate layer is a porous substrate that is immersed in an immersion-type coolant. A contact angle between the surface film layer and the immersion-type coolant is less than a contact angle between the heat dissipation substrate layer and the immersion-type coolant. A thickness of the surface film layer is less than an effective thickness of 5 ?m.

Abstract: A touch-based control device is operable to detect touch input over an entirety of the control device's exterior, including at regions of an exterior panel that (i) overlay portions of a circuit board where no touch sensors exist, and/or (ii) extend beyond a perimeter of a touch region or circuit board on which touch sensors are provided.

Abstract: This disclosure is directed to, in part, techniques for determining occupancy states of a vehicle over time and adjusting settings associated with the vehicle based at least in part on these occupancy states. For instance, an example vehicle may include an array of sensors that may generate sensor data for identifying an occupancy state of a vehicle. These sensors may include cameras, microphones, in-seat weight sensors, seatbelt sensors, door-latch sensors, and the like, which may be used to generate sensor data indicative of a current occupancy state of a vehicle. An occupancy state may include a number of occupants of the vehicle, the location of these occupants within the vehicle, the identity of these occupants, and/or the like.

Abstract: Techniques for using scoring algorithms utilizing containers for flexible machine learning inference are described. In some embodiments, a request to host a machine learning (ML) model within a service provider network on behalf of a user is received, the request identifying an endpoint to perform scoring using the ML model. An endpoint is initialized as a container running on a virtual machine based on a container image and used to score data and return a result of said scoring to a user device.

Abstract: The present invention relates to a transmission and reception method of a radio signal by a terminal in a wireless communication system. According to the present specification, disclosed is a method comprising the steps of: determining whether or not transmission of an uplink radio signal or reception of a downlink radio signal allocated to a terminal is possible on a slot configured to comprise at least one of one or more downlink symbols for downlink transmission, one or more flexible symbols and one or more uplink symbols for uplink transmission; and controlling the transmission of the uplink radio signal or the reception of the downlink radio signal on the basis of the determination. According to the present invention, the terminal can transmit the uplink radio signal even if the configuration of the slot is changed, and thus uplink radio signal transmission omission or unnecessary retransmission of the uplink radio signal can be prevented.

Abstract: A connected device at a client network implements a local data classification service for classifying data based on a data classification service of a remote provider network. The local data classification service receives a request to classify data at one or more data sources of the client network. The request is initiated from a client device of the client network according to a management interface for a data classification service of a remote provider network (e.g., using the same API request used by the remote classification service). The local data classification service obtains at least some of the data from the one or more data sources of the client network. The local data classification service classifies the obtained data according to different types of sensitivity using the data classification engine in the execution environment without the data being exposed outside of a data isolation boundary of the client network.

Abstract: The technology described herein relates to a visual communication system for a helmet mounted visual communication and navigation system. A visual communication system may include a pointing laser on a vision module pointing forward in a direction of a user's point of view (POV), a rear communication light configured to project light in a backward direction from the user's POV, a graphical user interface (GUI) on a heads up display (HUD), and user control buttons configured to control the pointing laser, the rear communication light, and elements of the GUI. Users of such a visual communication system may include emergency response personnel and critical workers, and the GUI may display various vision modes directed to situations that may arise out of an emergency response, military, law enforcement, public safety effort or mission.

Abstract: An industrial gateway device supports interactive feature engineering tools that guide a user through an intuitive process for configuring data analytics for key performance indicators (KPIs) of interest. A feature engineering interface renders an interactive model view that displays available data points such that the data points are organized hierarchically according to plant, machine, machine property, or other elements. The user can select, from this model view, data points having an impact on the KPI of interest. The interface also allows the user to define an executable script that defines a mathematical relationship between the selected data points and the KPI. This configuration yields an output model that defines a reduced set of data points to be collected and analyzed, as well as an executable script for assessing a state of the KPI as a function of the reduced data point values.

Abstract: An anti-fuse memory: an inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

Abstract: One or more virtual machines are launched at an application platform. At each of the one or more virtual machines, a machine learning model execution environment is instantiated for an instance of a machine learning model. A respective instance of the machine learning model is loaded to each machine learning model execution environment. Each loaded instance of the machine learning model is associated with an application programming interface (API) endpoint which can receive input data for the loaded instance of the machine learning model from a client device and return output data produced by the loaded instance of the machine learning model based on the input data.

Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

Abstract: Apparatuses and methods of overlay measurement are disclosed. An example apparatus includes first and second layers. The first layer includes a first alignment pattern that includes a first line extending in a first direction. The first line includes first, second and third segments. The second layer above the first layer includes a second alignment pattern including: a second line extending in the first direction above the first segment and having a first offset from the first segment in a second direction perpendicular to the first direction; a third line extending in the first direction above the second segment and having a second offset from the second segment in the second direction; and a fourth line extending in the first direction above the third segment and having a third offset from the third segment in the second direction. The first, second and third offsets are different from one another.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

Abstract: Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.

Abstract: A chip testing method and apparatus, and an electronic equipment are provided. The method includes: determining, according to pad distribution information of a target chip, positions of set state pads and positions of non-set state pads in the target chip, the set state pads being pads with set states, and the set states including a first state or a second state; determining a plurality of pad state setting schemes according to the positions of the set state pads and the positions of the non-set state pads, the pad state setting schemes including setting each of the non-set state pads to the first state or the second state; and determining a test voltage setting scheme satisfying a preset condition according to information of differential voltage pad pairs in each of the pad state setting schemes, the differential voltage pad pair comprising two adjacent pads in different states.

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

Abstract: The embodiment of the application provides a method of manufacturing a semiconductor structure, which comprises the following steps: forming a target layer, a first mask layer, an isolation layer and an intermediate layer sequentially on a substrate, wherein first trench is disposed in the intermediate layer in the first region and second trench is disposed in the intermediate layer in the second region; forming a fill layer, and the difference in the height between the top surface of the fill layer in the first region and in the second region is less than or equal to a first preset value; removing a portion of the fill layer in the first region until the top surface of the sacrificial layer is exposed; removing the sacrificial layer; and etching a portion of the target layer through the first opening, wherein the remaining target layer forms a target pattern.

Abstract: Reset operations impact data storage device latency. Every reset operation involves flushing cache data to the memory device and resetting the front end application specific integrated circuit (ASIC) accelerator/host interface module (HIM). Multiple resets that are performed consecutively waste valuable data storage device resources due to the duplication of the operations that every reset operation performs. Data storage device latency can be improved, as can data storage device idle time, by combining reset operations and removing duplicative operations. For example, for two different, but consecutive reset operations, the reset operations are performed by flushing the cache data and resetting the ASIC accelerator/HIM only once rather than repeat the operations for each reset operation. In so doing, the two reset operations complete reset operations faster than would otherwise occur.