Abstract: A method, system, and apparatus are disclosed herein for bridging a deterministic phase of instructions with a non-deterministic phase of instructions when those instructions are executed by a machine learning accelerator while executing a machine learning network. In the non-deterministic phase, data and instructions are transferred from off-chip memory to on-chip memory. When the transfer is complete, processing elements are synchronized and, upon synchronization, a deterministic phase of instructions is executed by the processing elements.

Abstract: Structural panels include a plurality of structural layers adhered together in a laminate, including a plurality of bamboo structural layers and at least one non-bamboo structural layer disposed between a first bamboo structural layer and a second bamboo structural layer of the plurality of bamboo structural layers. The first bamboo structural layer and the second bamboo structural layer of the plurality of bamboo structural layers are spaced apart by the at least one non-bamboo structural layer on opposite sides of a neutral plane extending through a center of the structural panel and parallel to the plurality of bamboo structural layers. Structural sections including wall sections, roof sections, and floor sections include one or more structural panels.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storing unit stores therein contract information indicating, with respect to each of a plurality of devices rented to a user and included in a system, an expiration time point at which a rental contract of each of the plurality of devices expires and communication channel information indicating inter-device communication channels between the plurality of devices. A processing unit determines, based on the contract information and the communication channel information, a second device to experience effect of expiration of the rental contract of a first device at a first time point amongst the plurality of devices, and outputs information indicating the effect on the second device.

Abstract: The technology relates in part to a segmented pipette tip adapter that includes a plurality of plate segments and a junction between adjacent plate segments. Each of the plate segments often includes a proximal surface, a distal surface, edges, one or more nozzles disposed on the proximal surface, and one or more tubular projections disposed on the distal surface. Each of the nozzles often includes a nozzle bore, each of the tubular projections often includes a tubular projection bore, each of the plate segments often includes a plate bore disposed at each of the nozzles, and each nozzle bore often is aligned with a tubular projection bore and a plate bore. Each junction often is between adjacent edges of a pair of adjacent plate segments.

Abstract: In one embodiment, an illustrative method herein may comprise: obtaining, by a device, a plurality of indications of errors experienced by a bot performing tasks, wherein each of the plurality of indications includes contextual information of a corresponding error; determining, by the device, correlated errors among the errors experienced by the bot; aggregating, by the device, contextual information of each of the correlated errors into aggregated contextual data; and providing, by the device, the aggregated contextual data with an error notification for a particular correlated error.

Abstract: A configurable Faraday shield is provided. The configurable Faraday shield includes a plurality of ribs. Each of the ribs can be spaced apart from one another along a circumferential direction. Furthermore, at least a portion of the configurable Faraday shield is movable between at least a first position and a second position to selectively couple the configurable Faraday shield to a radio frequency ground plane. When the at least a portion of the configurable Faraday shield is in the first position, the configurable Faraday shield can be decoupled from the radio frequency ground plane such that the configurable Faraday shield is electrically floating. Conversely, when the at least a portion of the configurable Faraday shield is in the second position, the configurable Faraday shield can be coupled to the radio frequency ground plane such that the configurable Faraday shield is electrically grounded.

Abstract: Technology is described for receiving an event notification produced by a source service. A negative cache may be searched for a cache entry for the event notification. The negative cache may be determined to not include the cache entry for the event notification. The event notification may be determined to satisfy a filter rule included in a filter rules table, which may indicate that the event notification is useful information for a destination service. The event notification may be transmitted to the destination service.

Abstract: In one embodiment, a device may receive a multicast path trace request for a multicast tree, wherein the device is a mid-node in the multicast tree. The device may perform, based on the device being a mid-node in the multicast tree, an upstream trace of network topology of the multicast tree from the device to a head-node of the multicast tree and a downstream trace of network topology of the multicast tree from the device to at least one tail-node. The device may generate an end-to-end visible topology of the multicast tree based on the upstream trace and the downstream trace. The device may provide the end-to-end visible topology of the multicast tree to an observability manager.

Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a first side, a second side vertically adjacent to the first side, a first inlet, a first cavity, and a first outlet. The first side of the cold plate comprises a first region, a second region, and a third region, wherein the second region is between the first region and the third region. In some embodiments, the semiconductor device is attached to the first region of the cold plate and the third region of the cold plate, and the first cavity extends along the second region of the cold plate.

Abstract: A voice controlled assistant has a housing to hold one or more microphones, one or more speakers, and various computing components. The housing has an elongated cylindrical body extending along a center axis between a base end and a top end. The microphone(s) are mounted in the top end and the speaker(s) are mounted proximal to the base end. The microphone(s) and speaker(s) are coaxially aligned along the center axis. The speaker(s) are oriented to output sound directionally toward the base end and opposite to the microphone(s) in the top end. The sound may then be redirected in a radial outward direction from the center axis at the base end so that the sound is output symmetric to, and equidistance from, the microphone(s).

Abstract: Systems, apparatuses, and methods related to a row hammer refresh operation are described herein. An example apparatus can include an array of memory cells of a memory device. The array of memory cells can include a plurality of dies and at least one of the plurality of dies is a row hammer die. The example apparatus can include a memory controller coupled to the array of memory cells. The memory controller can perform a number of operations on the array of memory cells. The memory controller can detect a quantity of accesses associated with the row hammer die and based on the number of operations performed. The memory controller can, in response to detection of a threshold quantity of accesses of a group of memory cells in the row hammer die, perform a refresh operation on a group of memory cells in an additional die of the plurality of dies.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: A vane assembly adapted for a gas turbine engine includes a first vane segment that extends circumferentially about an axis and a second vane segment. The second vane segment includes a band that extends circumferentially about the axis and a plurality of vanes coupled to the band and extending radially from the band.

Abstract: Systems and methods are provided for receiving a start location and a destination location, determining a road segment corresponding to the destination location, and identifying a node nearest the road segment corresponding to the destination location, whereby the node corresponds to a nearest left-hand node for a right-hand driving country or a nearest right-hand node for a left-hand driving country. The systems and methods further provide for generating a first route from the start location to the node nearest the road segment corresponding to the destination location, generating a second route from the node nearest the road segment corresponding to the destination location, to the destination location, and combining the first route and the second route to generate a final route. Thus, the final route comprises a route from the start location, through the node nearest the road segment corresponding to the destination location, to the destination location.

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Abstract: Systems and methods for natural language query processing and visualization. In embodiments, a structure associated with a dataset and a natural language question are obtained and provided to an AI model to request, from the AI model, a query that may be used for retrieving data from the dataset responsive to the natural language question. The query is received form the AI model and executed against the data in the dataset to retrieve data responsive to the natural language question. In embodiments, the data responsive to the natural language question is analyzed to determine one or more structural characteristics of the data responsive to the natural language question, and a graphical visualization of the data responsive to the natural language question is generated based on the one or more structural characteristics of the data responsive to the natural language question.

Abstract: Method for searching a hole pattern in image includes extracting, from an image where a hole pattern is formed, plural outline position candidates serving as candidates for plural positions where an outline of the hole pattern passes, generating, for each pixel in a region including the plural outline position candidates, a distance map which defines, for each of plural directions, a distance from each of the plural outline position candidates to each of pixels arrayed in a target direction of the plural directions, extracting a candidate for a center pixel of the hole pattern by using the distance map generated for each direction, and searching, in the plural outline position candidates, a group of outline position candidates which satisfies a predetermined condition in the case of using the candidate for the center pixel as a starting point, as plural outline positions where the outline of the hole pattern passes.

Abstract: Embodiments securely control an electronic asset. In some embodiments, a computer-implemented method of securely controlling an electronic asset includes identifying an asset NFT pertaining to the electronic asset. An ownership status of the electronic asset is computationally evaluated according to a proof of ownership provided by an owner node paired with the electronic asset. Responsive to evaluating the ownership status of the electronic asset, the asset NFT is bound with a representation of an identity of the owner node or of an authorized user node paired with the electronic asset. The bound representation of the identity and the asset NFT are registered on a blockchain associated with the electronic asset. A task is computationally performed involving the electronic asset, and the bound representation of the identity, and the electronic asset is securely controlled, in response to receiving a task request from the owner node or the authorized user node.