Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: An equalization system (18) that reduces inter-symbol interference in an input signal (220) includes a variable gain amplifier (430), and one or more peaking amplifiers (432) that are connected in series to the variable gain amplifier (430). The variable gain amplifier (430) receives the input signal (220) and scales the input signal (220) while each peaking amplifier (432) can be selectively controlled to selectively adjust a peaking gain (326) and a peaking corner frequency (328). Additionally, the equalization system (18) can include a PTAT bias generator (434) that provides a PTAT bias current to one or more of the peaking amplifiers (432) to maintain a transconductance of one or more of the peaking amplifiers (432) substantially constant as temperature changes. With this design, the equalization system (18) provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: A display device for indicating connection statuses of a communication channel between two systems is disclosed, the communication channel having a plurality of communication links. The display device comprises a detecting circuit coupled to the communication channel for detecting a plurality of link statuses of the communication links; an indicator controller coupled to the detecting circuit for determining the connection statuses of the communication channel according to the link statuses; and an LED indicator coupled to the indicator controller for displaying in a plurality of statuses according to the connection statuses from the indicator controller; wherein the connection statuses comprise a first connection status indicating that all the link statuses are “ON”, a second connection status indicating that all the link statuses are “OFF”, and a third connection status indicating that at least one of the link statuses is “ON” and at least one of the link statuses is “OFF”.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Abstract: A lancet driver is provided wherein the driver exerts a driving force on a lancet during a lancing cycle and is used on a tissue site. The driver of includes a drive force generator for advancing the lancet along a path into the tissue site, and a sensor configured to detect lancet position along said path during the lancing cycle.

Abstract: Inertial sensor having a body with first and second cavities on opposite sides thereof, a sensing element in the first cavity, electronic circuitry in the second cavity, electrical conductors interconnecting the sensing element and the circuitry, and leads connected electrically to the circuitry and extending from the body for mounting the sensor and making connections with the circuitry.

Abstract: A data outputting apparatus, includes a box capable of storing data in a sorted manner, an outputting portion for outputting the data stored in the box, a data number setting portion for setting the number of data to be stored in the box, and a controller for making the outputting portion output the data stored in the box when the number of data stored in the box has reached the set number of data.

Abstract: The protection of multi-segment pseudowires by utilizing pre-computed backup paths is disclosed herein. Disclosed embodiments include methods that establish at least one backup path for multi-segment pseudowires, the establishing being performed prior to detection of failure in the primary path. Upon detecting a path failure, the detected failure is signaled to the head-end, a pre-computed backup path is chosen, and the chosen backup path is signaled to the tail-end. In other disclosed embodiments, apparatus are configured to establish, prior to detection of failure in the primary path, at least one backup path for the multi-segment pseudowire. Networks can be configured to signal a detected failure to the head-end; choose a pre-computed backup path; and signal the backup path to the tail-end.

Abstract: A method and apparatus for centralized control of a network is described. The network includes a number of nodes. The method includes creating a database and storing the database on a master node of the network. The database contains topology information regarding a topology of the network. Each of the nodes is coupled to at least one other of the nodes, with the master node being one of the nodes.

Abstract: A MIMO system with Diversity processing is provided having Turbo Codes Decoders for computing orthogonal signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the Wireless system to deliver data rates from up to 200 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A Turbo Codes Decoder block is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for pipeline operations.

Abstract: An illuminating brick includes a block and at least one light-emitting element mounted in the brick. The brick has a top face, a bottom face and a plurality of lateral side surfaces interconnecting the top and bottom faces. The at least one light-emitting element is engaged in and optically coupled to at least one of the bottom face and lateral side surfaces. The lateral side surfaces and the bottom face are configured for reflecting and directing light emitted from the at least a light-emitting element to exit through the top face.

Abstract: A method is provided for creating a series of digital signal processing (DSP) filters to improve the transient response of a loudspeaker, wherein the loudspeaker is formed of multiple components. The method includes generally six steps. The first step involves identifying a substantially linear, time-invariant, and spatially-consistent loudspeaker mechanism causing transient response distortion. The second step involves characterizing the identified mechanism. The third step involves determining the characterized mechanism's two-port response. The fourth step involves establishing a target response for the characterized mechanism. The fifth step involves calculating an ideal filter to achieve the target response. The sixth step involves designing a cost-reduced filter based on the ideal filter.

Abstract: A method for processing multiple data packets includes receiving from a network interface, at a packet management unit (PMU), a data packet for processing, and determining whether to store or drop the data packet. The method further includes queueing the data packet in a queue within a queueing system and preloading a portion of the data packet into a context from a pool of contexts in a stream processing unit (SPU). The queued data packet referenced by the context is processed by the SPU and outputted to the network interface.

Abstract: An image sensor includes a color filter array, sense amplifiers, multiplexing circuitry, and an output. The color filter array acquires image data using an array of M columns and N rows of pixels. The sense amplifiers are coupled to the color filter array for reading out image data from the color filter array. The multiplexing circuitry couples the sense amplifiers to the color filter array, wherein each sense amplifier is time shared across multiple columns and multiple rows. The output is coupled to receive the image data from the sense amplifiers and output the image data off-chip.

Abstract: A technique distinguishes between link and node failure using bidirectional forwarding detection (BFD) in a computer network. According to the novel technique, a BFD session is established over a first link between a monitoring node and a first interface of a monitored node. In addition, one or more novel unidirectional BFD (uBFD) sessions from one or more corresponding other interfaces of the monitored node to the monitoring node (e.g., as configured by the monitored node to detect its failure), the one or more uBFD sessions traversing links other than the first link (e.g., “not-via” the monitored node) are established, the one or more uBFD sessions traversing links other than the first link (e.g., “not-via” the monitored node). For instance, the one or more uBFD sessions correspond to one or more line cards of the monitored node. In response to detecting a lack of connectivity resulting from, e.g.