Abstract: An electrode structure of an LED includes an adhesion layer and a bond pad layer. The adhesion layer is stacked on the LED. The bond pad layer is stacked on the adhesion layer. The bond pad layer includes at least two first metal layers, at least two second metal layers and an outermost gold layer sequentially and alternately stacked. The first metal layers are selected from the group consisting Al and an Al alloy, and the second metal layers are selected from the group consisting of Ti, Ni, Cr, Pt, Pd, TiN, TiW, W, Rh and Cu. Thus, the main structure of the bond pad layer is a stacked structure of the first metal layers and the second metal layers. The first metal layers may be selected from a low-cost material, and the second metal layers improve issues of inadequate hardness and electromigration of the first metal layers.

Abstract: A transparent conductive layer structure for an LED is provided. The LED includes a reflecting layer, an N-type electrode, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a current block layer, a transparent conductive layer and a P-type electrode that are stacked on a substrate. The current block layer is disposed between and separates the P-type electrode and the P-type semiconductor layer. The transparent conductive layer is disposed between the P-type electrode and the current block layer, and connects to the P-type electrode and the P-type semiconductor layer. At a region corresponding to the P-type electrode, a plurality of holes are disposed at the transparent conductive layer to reduce an area of and hence an amount of light absorbed by the transparent conductive layer, thereby increasing light extraction efficiency of excited light from the light emitting layer and enhancing light emitting efficiency of the LED.

Abstract: A flip chip light-emitting diode (LED) package structure includes a circuit board, an electrical conducting layer and a plurality of flip chip light-emitting elements. The circuit board includes a bearing surface. The electrical conducting layer is formed on the bearing surface, and includes a plurality of electrical connection regions independent of each other. Each flip chip light-emitting element includes a p-type electrode and an n-type electrode. The p-type electrodes and the n-type electrodes of the flip chip light-emitting elements are electrically connected to the electrical connection regions, so that the flip chip light-emitting elements are electrically connected in series to form a package structure. During packaging of the flip chip light-emitting elements, the structure formed by the serial connection forms a circuit that can withstand a high voltage, and further reduce the current.

Abstract: A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: A method for fabricating a vertical light-emitting diode comprises forming a stack including a plurality of epitaxial layers on a patterned first substrate, placing a second substrate on the stack, removing the first substrate to expose the first surface, planarizing a first surface of the stack that was in contact with the patterned first substrate and has a pattern corresponding to a pattern provided on the first substrate to form a planarized second surface, and forming a first electrode in contact with a side of the second substrate that is opposite to the stack, and a second electrode in contact with the second surface of the stack. A roughening step can be performed to form uneven surface portions on a region of the second surface for improving light emission through the second surface of the stack.

Abstract: The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.

Abstract: The present invention discloses a surface roughening method for an LED substrate, which uses a grinding technology and an abrasive paper of from No. 300 to No. 6000 to grind the surface of a substrate to form a plurality of irregular concave zones and convex zones on the surface of the substrate. Next, a semiconductor light emitting structure is formed on the surface of the substrate. The concave zones and convex zones can scatter and diffract the light inside LED, reduce the horizontally-propagating light between the substrate and the semiconductor layer, decrease the probability of total reflection and promote LED light extraction efficiency.

Abstract: A group III-nitride semiconductor Schottky diode comprises a conducting substrate having a first surface, a stack of multiple layers including a buffer layer and a semiconductor layer sequentially formed on the first surface, wherein the semiconductor layer comprises a group III nitride compound, a first electrode on the semiconductor layer, and a second electrode formed in contact with the first surface at a position adjacent to the stack of multiple layers. In other embodiments, the application also describes a method of fabricating the group III-nitride semiconductor Schottky diode.

Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.

Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and form a plurality of convex zones; a semiconductor layer structure is epitaxially grown on the element regions and carved regions of the substrate; the semiconductor layer structure on the element regions is fabricated into a LED element with a photolithographic process.

Abstract: A method for self bonding epitaxy includes forming a passivation layer on a substrate surface of a semiconductor lighting element; etching to form recesses and protrusive portions with the passivation layer located thereon; starting forming epitaxy on the bottom surface of the recesses; filling the recesses with an Epi layer; then covering the protrusive portions and starting self bonding upwards the epitaxy to finish the Epi layer structure. Such a self bonding epitaxy growing technique can prevent cavity generation caused by parameter errors of the epitaxy and reduce defect density, and improve the quality of the Epi layer and increase internal quantum efficiency.