Abstract: A method of determining a timing relationship between modules on a chip, each module being timed by an initiator. The timing relationship being determined on the basis of the power consumptions over time of the initiators and may be determined on the basis of e.g. a sum of the power consumptions or more complex calculations also incorporating the signal path or power delivery network, whereby a voltage drop or current drawn at a position in the chip may be determined. In addition, a parameter, which may be the sum or voltage drop, current or e.g. an energy content within a frequency range, may be determined. This parameter may be varied by e.g. providing different timing relations of initiators, in order to minimize the parameter or adapt it to a requirement as a maximum peak value, maximum difference between max and min peaks, a flatness criteria or the like.
Type:
Grant
Filed:
April 14, 2009
Date of Patent:
March 18, 2014
Assignee:
Teklatech A/S
Inventors:
Tobias Bjerregaard, Christian Place Pedersen, Martin Schwalbe Lohmann, Mikkel Bystrup Stensgaard
Abstract: A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier.
Abstract: A system and a method of transmitting data from a first device to a second device, both devices receiving a clock signal, the first device acting on a first flank of the clock signal and the second device acting on a second flank of the clock signal. A chain of this type of devices may be used, where every second device acts on the first flank and the others on the second flank. In this manner, the data transport may be provided at the clock frequency while allowing backpressure.
Abstract: A method of determining a timing relationship between modules on a chip, each module being timed by an initiator. The timing relationship being determined on the basis of the power consumptions over time of the initiators and may be determined on the basis of e.g. a sum of the power consumptions or more complex calculations also incorporating the signal path or power delivery network, whereby a voltage drop or current drawn at a position in the chip may be determined. In addition, a parameter, which may be the sum or voltage drop, current or e.g. an energy content within a frequency range, may be determined. This parameter may be varied by e.g. providing different timing relations of initiators, in order to minimize the parameter or adapt it to a requirement as a maximum peak value, maximum difference between max and min peaks, a flatness criteria or the like.
Type:
Application
Filed:
April 14, 2009
Publication date:
April 28, 2011
Applicant:
Teklatech A/S
Inventors:
Tobias Bjerregaard, Christian Place Pedersen, Martin Schwalbe, Mikkel Bystrup Stensgaard
Abstract: A method and a system of controlling access of data items to a shared resource, wherein the data items each is assigned to one of a plurality of priorities, and wherein, when a predetermined number of data items of a priority have been transmitted to the shared resource, that priority will be awaiting, i.e. no further data items are transmitted with that priority, until all lower, non-awaiting priorities have had one or more data items transmitted to the shared resource. In this manner, guarantees services may be obtained for all priorities.