Abstract: A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency.

Abstract: A linearizer and method. In a most general embodiment, the inventive linearizer includes a characterizer coupled to an input to and an output from said circuit for generating a set of coefficients and a predistortion engine responsive to said coefficients for predistorting a signal input to said circuit such that said circuit generates a linearized output in response thereto. In a specific application, the circuit is a power amplifier into which a series of pulses are sent during an linearizer initialization mode of operation. In a specific implementation, the characterizer analyzes finite impulse responses of the amplifier in-response to the initialization pulses and calculates the coefficients for the feedback compensation filter in response thereto. In the preferred embodiment, the impulse responses are averaged with respect to a threshold to provide combined responses. In the illustrative embodiment, the combined responses are Fast Fourier Transformed, reciprocated and then inverse transformed.

Abstract: A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.

Abstract: A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.

Abstract: A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

Abstract: An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Abstract: A digitally trimmed current source. The novel current source includes a first circuit for generating a current in response to an applied voltage and a resistance variable in response to a control signal, and a second circuit for supplying the control signal. The first circuit includes a resistive network comprised of a plurality of resistors; a plurality of switches, each switch coupled to one of the resistors and adapted to selectively switch the resistor in and out of the resistive network in response to the control signal; and a transistor adapted to apply a voltage across the resistive network to generate a current.

Abstract: A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.

Abstract: An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in the output signal. The second circuit includes a bootstrapping circuit adapted to regulate the voltages across any transistors in the signal path such that the voltages remain constant. In an illustrative embodiment, the second circuit bootstraps the voltages across a PMOS current source that acts as the load to an input stage, as well as a Darlington pair in an output stage of the amplifier.

Abstract: Multi-layer metal-shielded monolithic transmission lines are formed in side-by-side arrangement by depositing parallel planar thin film, conductive layers, separated by nonconductive separator layers to form a stack of alternating conductive and nonconductive layers. The conductive layers form a top and a bottom conductive plane and establish a mutually registered selected width of the stack. A center conductive layer has laterally spaced apart conductive strips separated by nonconductive spacer layers. The two laterally terminal of the conductive strips are spaced at the selected width. Each of the nonconductive separator layers provides a plurality of elongated vias between the two lateral terminals of the three conductive strips and the conductive planes.

Abstract: A signal processing system and method. The inventive system includes a first circuit for distributing an input signal between two or more channels in a current mode of operation. A second circuit is disposed in each of the channels for processing the input signal and providing an output signal in response thereto. A third circuit is provided to combine the signals output by the processing circuit. A fourth circuit is included for controlling the first and the third circuits. In a specific illustrative embodiment, the system further includes a radio frequency stage for downconverting a received signal and providing the input signal in response thereto. In the specific embodiment, the first circuit includes a mixing circuit. The mixing circuit includes Gilbert cells and circuitry for providing automatic gain control for each of the channels individually. The Gilbert cells and the automatic gain control circuitry are driven by a transconductance amplifier and therefore operate in a current mode.

Abstract: A crosspoint switch architecture (10). The inventive architecture (10) includes a monolithic substrate (11) on which a plurality (N) of electrical inputs are provided. In addition, a plurality (M) of electrical outputs are provided on the substrate (11). A switch is disposed on the substrate (11) for selectively interconnecting the inputs to the outputs and a control circuit (16) is disposed on the substrate (11) for controlling the switch. The switch comprises M, N to 1, multiplexers (14), each multiplexer (14) being adapted to receive each of the N electrical inputs. In the illustrative embodiment, each of the N inputs to each of the multiplexers is received through a respective one of N switchable amplifiers (18). The output of each amplifier (18) is provided to a respective one of N switchable isolation buffers (19). The outputs of the buffers (19) are summed and buffered to provide the output of each multiplexer (14).

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.

Abstract: A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2 -I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths.

Abstract: A system and method for sampling and holding a signal. The invention includes a novel input circuit for a track and hold circuit comprising a circuit Q1 for receiving an input signal including an input node, a first output node N1, and a path connecting the input and output nodes; a current switching circuit for applying a first current to the node N1 during a first mode of operation but not during a second mode; and a current source for applying a second current to the node N1 during both of the first and second modes. The value of the first current is determined such that the total current in the path is constant during the first and second modes. In an illustrative embodiment, the first mode is a track mode and the second mode is a hold mode.

Abstract: An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the current source and the current sink; and a control circuit for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as a voltage difference between a fixed reference voltage and a pin output voltage of a device under test.

Abstract: A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.

Abstract: An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal.

Abstract: A system and method for effecting wideband image rejection. In a receiver implementation, the inventive method includes the steps of receiving a first signal in a first frequency band and generating in-phase and quadrature signals therefrom. The phase of the in-phase signal is shifted to provide a second signal and the phase of the quadrature signal is shifted to provide a third signal. A predetermined phase relationship is thereby effected between the second and the third signals. The second and third signals are then summed to provide an output signal which has minimal interference from a mixing signal. In an illustrative receiver application, the phase shifting is achieved via the use of all pass networks. Each of the all pass networks include a differential amplifier having first and second input terminals. The first and the second terminals are connected to a first end of first and second resistive elements, respectively.

Abstract: A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution.