Abstract: Apparatus (100) and accompanying methods for accurately simulating a digital facility, including impairments, in a public switched telephone network (PSTN). The invention is particularly suited for precisely emulating, as part of that facility, a line card within a channel bank including a hardware coder-decoder (CODEC) circuit contained therein, but without using an actual CODEC. Specifically, to properly emulate a digital facility, including such a line card, impairments, which need to be emulated, arise not only from the network facility itself but also from the line card. The former include robbed bit signaling (RBS), digital trunk loss and network delay. The latter include intermodulation distortion (IMD), analog loss and echo. To achieve very precise emulation, the simulator implements IMD and network impairments digitally but with the former impairment being processed at much higher, i.e., oversampled, (illustratively 32 kHz) sample rate relative to the sample rate for the latter impairments (e.g.

Abstract: Circuitry for transforming a transfer function characteristic into a specified input impedance includes: a hybrid arrangement having input, transmit, receive and balance ports; and a two-port network connected from the transmit to receive ports of the hybrid. The relation between the input impedance at the input port to the network transfer function is expressible as a function of the actual impedance seen looking into the two-wire input port of the hybrid, and the desired impedance to be simulated.

Abstract: A Bit Error Rate (BER) test arrangement, composed of two autonomous BER test systems, effects the full-duplex testing of a pair of co-located modems terminating a simulated transmission link by utilizing a single processor to control each independent BER test system and a buffer storage device, preferably a dual-port random access memory and a multiple access memory serving each of the test systems, to post information communicated between the controller processor and each of the test systems. This arrangement minimizes duplication of circuitry by assigning basically identical processing operations of the individual test systems to the single processor.