Abstract: An anti-tank trap (1) is constituted by a support (2), a military payload (3), an igniter (4) and a sight (5). The firing on the target is carried out at the time t.sub.d in a plane .DELTA.. The invention is characterized by the following chronological series of stages:first detection by FM/CW radar (lobes 11) and establishment of a first map ERA.sub.ref,second infra-red detection (IR) at t.sub.2 (plane V or V'),third IR detection at t.sub.1 (plane U or U'),computation of: t.sub.1 -t.sub.2 and of the angular velocity d.gamma./dt of the target,fourth detection by FM/CW radar (ERA.sub.m),measurement of the range d.sub.c and of the size of the target (ERA.sub.m -ERA.sub.ref),analysis of the target, firing decision, computation of t.sub.d and triggering at t.sub.d of the military payload.Application to an anti-tank trap.

Abstract: A baseband-controlled passband equalizing arrangement comprises a passband correction circuit for the data signals transmitted by modulating a carrier frequency, a first demodulation circuit which cooperates with a carrier recovery circuit for converting these carrier-modulated data signals into baseband signals, and a control circuit acting on the variable elements provided in the passband correction circuit in response to an estimated error of the baseband signals. The passband correction circuit produces a passband output signal v(t), which is a continuous function of the time t, in response to a passband input signal x(t), which is a continuous function of the time t, in accordance with the relation: ##EQU1## where r.sub.m, .psi..sub.m, .rho..sub.j, .phi..sub.j are variable elements, and .tau..sub.j, .tau..sub.m are fixed delays and M, N are constants.

Abstract: An arrangement by which a sinusoidal wave is modulated in phase and amplitude in response to groups of bits includes an input (1) for receiving the groups of bits, a phase shifting circuit (5, 7) for producing two phase-shifted components of the wave and a modulating circuit for modulating the amplitude of the two components as a function of the groups. The modulating circuit includes a ROM (25), addressed by part of the n bits of the bit groups for producing an initial amplitude value, and a calculating unit (30) for obtaining final amplitude values by changing original values according to the remaining part of the bits of the bit groups.

Abstract: An arrangement for measuring and cancelling bias distortion is designed for correcting the distortion of the binary signals which do not comprise any zero-frequency spectral components, automatically and cyclically measures said distoration (DM) by consecutive analyses of the binary data at a sampling frequency (SCK) which is a multiple of the data frequency in order to determine the sign and the quantized value of the distortion (UDC). It includes distortion cancelling means (CC) which augment the length of the binary elements selectively as a function of the sign of the distortion and proportionally to the quantized value of the said distortion and this is done until the distortion is cancelled completely.

Abstract: Echo canceler associated with a modem utilizing amplitude and phase modulation of a carrier, the echo canceler comprising adaptive filters (16-1) to (16-p) producing signals which are combined in an adder (15) for forming a synthetic echo signal .epsilon.(n). The coefficients of these filters are adjusted to minimize the mean square value of the residual echo signal e(n)=.epsilon.(n)-.epsilon.(n), where .epsilon.(n) is the echo received. The echo canceler comprises a code conversion circuit (17) which receives a signal D(n) characterizing in each modulation interval the amplitude and phase state of the carrier to be transmitted and which produces distinct configurations of several numbers of values +1, -1 or 0, said distinct configurations corresponding to the distinct possible states of the carrier to be transmitted such that elementary signals D.sub.1 (n) to D.sub.p (n) are formed which are mutually independent in the mean and which are applied to the filters (16-1) to (16-p).

Abstract: An arrangement for cancelling the composite echo signal formed by, for example, a linear component and a variable-phase component, comprises a linear echo canceller and a variable phase echo canceller, the difference circuits of these echo cancellers being arranged in cascade. The adjustable signal processing arrangements of each echo canceller are controlled for minimizing a predetermined function (mean square value or time average of this means square value), either of a residual echo signal appearing at the output of the difference circuit of this echo canceller itself or of a residual echo signal appearing at the output of the cascade arrangement of the difference circuits. In all cases the signal at the output of the linear echo canceller contains only a residual variable-phase signal which can be compensated for by the variable-phase echo canceller.

Abstract: This encoding arrangement has an input (12) for receiving a sequence of samples to be encoded, an output for supplying encoded samples, processing circuits, more specifically:a differential circuit (20) for producing differential samples between the samples to be encoded and prediction samples,a prediction circuit (22) to produce prediction samples from the encoded samples.It is characterized in that the processing circuits are separated into encoding units (E1, E2, E3 and E4) for each effecting a processing operation on each sample to be encoded and that an interleaving member (60) is provided to convert the sequence of samples to be encoded into a sequence of interleaved samples so as to ensure that all the processing operations to be effected on a sample are indeed effected.

Abstract: An analogue scrambling system with dynamic band permutation in which the speech signal is filtered (1), sampled (2) at the rate f.sub.e, digitized (3), transformed by means of an analysis filter bank (4) into N sub-band signals sampled at f.sub.e /N and transferred in a permuted order to a synthesis filter bank (13) accomplishing the calculations of the scrambled signal sampled at the rate f.sub.e. A set of permutations is protected in a memory (8) and a scrambling with dynamic permutation in time is obtained by changing the read addresses of the memory. The scrambled signal reconverted into an analogue signal (14, 15) is transmitted through an analogue channel to an unscrambler where it is preprocessed so that the synchronizing and equalizing functions are accomplished and where the accomplished processes are identical with those accomplished in the scrambler, the difference being that the permuted order of the N sub-band signals is restored.

Abstract: A processor formed from a signal processing unit operating according to instructions transmitted by a bus line, including a slave section provided with an address/data port for connection to a master signal processing circuit; a first buffer register in which data coming from the master processing circuit via the address/data port can be written and read in order to be processed by the processing unit, a second buffer register in which the data processed by the processing unit can be written, then read in order to be directed via the address/data port to the master processing circuit and a sequential control circuit so that access to these buffer registers is allocated in turn to the processing unit and to the master processing circuit. A master section is also provided intended to be connected to at least one slave circuit.

Abstract: The apparatus for detecting and discriminating phase jumps in a periodic signal comprises, arranged in cascade between an input terminal (1) and an output terminal (2), a frequency converter (3) transforming the frequency spectrum of the input signal e(t) containing a line at the frequency f.sub.e in a continuous band spectrum whose frequency is centered around f.sub.e, an interrupter (4), a resonator (5) having a resonant frequency f.sub.0 near f.sub.e and a phasemeter (6) having detection and discrimination means. The ensemble of these elements (3-6) is controlled by a sequencer (7) which, at each period .alpha. such that .alpha.=t.sub.1 +t.sub.2, allows the phase detection and the discrimination of each phase jump of a predetermined value .DELTA..phi..sub.e which may be contained in the input signal at the frequency f.sub.e.

Abstract: Method of adjusting the interstation delay in an information transmission system comprising a large number of relay stations arranged in cascade and utilizing in one transmission direction the TDMA method, and a system to which such a delay adjusting method is applied.This method of adjusting the interstation delay in an information transmission system utilizing the TDMA principle can be advantageously used when the system comprises a large number of relay stations in a cascade arrangement. An adjusting range is imposed on the delay to be allocated to the transmission of data in order to avoid information jumps which may provoke overlapping on reception of these data. The adjustment of the delay is effected by starting with the relay station nearest to the central station, then the following relay station etc., and ending with the adjustment of the terminal station involved.

Abstract: An echo canceller designed to cancel an echo signal [g(t)] generated in a send path (7) by a signal [f(t)] applied to a receive path (1) contains a subtractor (9) whose positive terminal receives a signal derived from the echo signal and whose negative terminal receives the output signal from a transversal filter (10) provided with means (12) for adjusting the filter coefficients in such a way that the component due to the echo signal is cancelled at the output of the subtractor (9).This echo canceller comprises a delta encoder (14) for encoding at a sampling rate 1/T the signal f(t) entering the receive path (1) and for supplying at the input of the transversal filter (10) a delta-encoded signal (.DELTA.F.sub.n), a circuit (22) for forming at the sampling rate 1/T the difference signal (d.sub.

Abstract: Clock recovery arrangement suitable more specifically for an information transmission system using the TDMA principle in one transmission direction.A clock recovery arrangement (24, 13) employed in an information transmission system comprised of a central station (1) and remote stations (2, 3, 4, 5, . . . ). Each station has at least one transmitter circuit (11, 21, 23, 31, 41, 51) and one receiver circuit (12, 20, 22, 30, 40, 50). The information components are time-division muliplexed in the direction from the central station to the remote stations and are transmitted in accordance with the TDMA principle in the other direction. The clock signal H of the multiplex direction is used in the TDMA direction to set the frequency of a first phase-locked loop, while a second loop ensures a fast phase reset. This clock recovery arrangement constituted by this dual loop thus satisfies the requirements as regards precision and reduction of the residual jitter.

Abstract: In a signal analysing and synthesizing filter bank system, the analysing bank receives a signal sampled at the rate f.sub.e and produces N contiguous subbank signals sampled at the rate f.sub.e /N. From the subband signals the synthesizing bank must recover the incoming signal. These filter banks are formed by modulation of a prototype filter by sinusoidal signals which, for subband k (O.ltoreq.k.ltoreq.N=1), have a frequency (2k30 1)f.sub.e /(4N) and respective phases +(2k+1).pi./4 and -(2k+1).pi./4 for the analysing and synthesizing banks. These signals are furthermore delayed by a time delay (N.sub.c -1)/2f.sub.e), where N.sub.c is the number of coefficients of the prototype filter.

Abstract: A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a loop circuit having an instruction counter which counts execution of the instructions in the loop sequence and produces an end-of-sequence signal upon each completion of the loop, a register which refreshes the program counter with the address of the first instruction in the loop in response to each end-of-sequence signal, and a loop counter which counts the number of completions of the loop and delivers a signal indicating the end of the loop portion of the entire program and enabling the program counter to continue on with the rest of the program. The delay in loop execution permits initializing of registers in the data processor so as to permit pipeline execution of the loop instruction.

Abstract: Echo canceler associated with a modem utilizing amplitude and phase modulation of a carrier, the echo canceler comprising adaptive filters (16-1) to (16-p) producing signals which are combined in an adder (15) for forming a synthetic echo signal .epsilon. (n). The coefficients of these filters are adjusted to minimize the mean square value of the residual echo signal e(n)=.epsilon.(n)-.epsilon.(n), where .epsilon. (n) is the echo received. The echo canceler comprises a code conversion circuit (17) which receives a signal D(n) characterizing in each modulation interval the amplitude and phase state of the carrier to be transmitted and which produces distinct configurations of several veral numbers of values +1, -1 or 0, said distinct configurations corresponding to the distinct possible states of the carrier to be transmitted such that elementary signals D.sub.1 (n) to D.sub.p (n) are formed which are mutually independent in the mean and which are applied to the filters (16-1) to (16-p).

Abstract: Apparatus for controlling the transmission power of a transmitting station over a digital radio communication channel, based on information relating to the level of the signal received at a receiving station and information relating to the quality of such received signal relative to a predetermined error rate. The signal level information and signal quality information is derived by respective threshold measurement devices in the receiving station, and is transmitted back to the transmitting station over a return channel. The transmitting station comprises means for effecting combined processing of such information to derive a control signal which controls means for increasing or decreasing the transmitting power over a dynamic adjustment range. In a first part of such dynamic range such control is based only on the information relating to received signal level, and over a second part of such range such control is additionally based on the quality of the received signal.

Abstract: A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.

Abstract: An arrangement ensuring the change-over of two channels through which the same digital information is conveyed with automatic data alignment over a .+-.3.5 bit range comprises for each channel an array of buffer stores operating at a write rate H.sub.i /N.sub.i (where i=1, 2), an oscillator operating at a rate H which provides reading of the buffer stores at the rate H/N and being synchronized in phase-opposition with one or the other of the write rates, and a logic comparator controlling the write rates H.sub.i /N.sub.i, the routing of the write rates to the input of the oscillator, as well as a change-over switch for the data.In the buffer store of the channel assumed to be the one whose quality degrades, the data are converted into N parallel streams at the rate H.sub.2 /N and are read at the rate H/N of the oscillator. In the other channel, the write rate of the buffer store is forced to the rate H.sub.

Abstract: A system for transmitting information between at least two stations the information originating from free or engaged channels in a multiplex frame, each station comprising at least one transmitting circuit and one receiving circuit powered from a power supply, and means for detecting the free and engaged channels to provide a procedure for establishing a multiplex formed by an elementary frame in which the engaged channels are grouped side-by-side in the elementary frame and means for reducing the power consumption of the transmitting and receiving circuits.